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| 型號(hào)： | XC4003E-4PC84I |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| 中文描述： | FPGA, 100 CLBS, 2000 GATES, 111 MHz, PQCC84 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 75K |
| 代理商： | XC4003E-4PC84I |
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R
February 11, 2000 (Version 1.8)
6-105
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted. The following guidelines reect worst-case values over the recommended operating conditions.
Speed Grade
-4
-3
-2
-1
Units
Description
Symbol
Device
Max
Full length, both pull-ups,
inputs from IOB I-pins
TWAF
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
9.2
9.5
12.0
12.5
15.0
16.0
17.0
18.0
5.0
6.0
7.0
8.0
9.0
11.0
13.9
16.9
5.0
6.0
7.0
8.0
9.0
11.0
13.9
16.9
4.3
5.1
6.0
6.5
7.5
8.6
10.1
–
ns
Full length, both pull-ups,
inputs from internal logic
TWAFL
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.0
12.5
14.0
16.0
18.0
19.0
20.0
21.0
7.0
8.0
9.0
10.0
11.0
13.0
15.5
18.9
7.0
8.0
9.0
10.0
11.0
13.0
15.5
18.9
5.5
6.4
7.0
7.5
8.5
10.0
11.8
–
ns
Half length, one pull-up,
inputs from IOB I-pins
TWAO
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
10.5
13.5
14.0
16.0
17.0
18.0
19.0
6.0
7.0
8.0
9.0
10.0
12.0
15.0
17.6
6.0
7.0
8.0
9.0
10.0
12.0
15.0
17.6
5.1
6.0
6.5
7.0
7.5
10.0
11.8
–
ns
Half length, one pull-up,
inputs from internal logic
TWAOL
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
12.0
12.5
14.0
16.0
18.0
19.0
20.0
21.0
8.0
9.0
10.0
11.0
12.0
14.0
16.8
19.6
8.0
9.0
10.0
11.0
12.0
14.0
16.8
19.6
6.0
7.0
7.6
8.4
9.2
10.8
12.6
–
ns
Note 1: These delays are specied from the decoder input to the decoder output.
Note 2: Fewer than the specied number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but
increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.
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