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參數(shù)資料
| 型號： | XC3S50A-5FTG256C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPARTAN-3A FPGA 50K 256FTBGA |
| 產(chǎn)品培訓模塊： | Extended Spartan 3A FPGA Family |
| 產(chǎn)品變化通告： | Package Substrate Change 20/Oct/2008 |
| 標準包裝： | 90 |
| 系列： | Spartan®-3A |
| LAB/CLB數(shù)： | 176 |
| 邏輯元件/單元數(shù)： | 1584 |
| RAM 位總計： | 55296 |
| 輸入/輸出數(shù)： | 144 |
| 門數(shù)： | 50000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 供應商設備封裝： | 256-FTBGA |
| 其它名稱： | 122-1721 XC3S50A-5FTG256C-ND |
The Programmable Logic
Challenge of I/O Intensive
Designs
Traditional FPGAs are proportionate
between logic and I/O not being cost-
effective for I/O intensive designs
System designers need to quickly adapt
to fast-evolving I/O standards
High volume consumer applications
require low-cost and robust security
solutions
The Xilinx FPGA Solution
The Spartan-3A FPGAs were designed
for applications where I/O count and
capabilities matter more than logic density
The Spartan-3A platform delivers up to
502 I/Os with support for industry-leading
26 popular and emerging I/O standards
The industry’s first 90nm FPGA electronic
ID - Device DNA serial number provides
a cost-effective, robust mechanism to help
protect against reverse-engineering,
cloning and overbuilding
Xilinx is driving the multiple domain-optimized platforms for highly efficient and
optimal design solutions, instead of forcing inefficient, one-size-fits-all solutions on
significantly varying application requirements.
Spartan-3A Platform Key Features
Standard Low-Cost Features
The Spartan-3A FPGA platform is a full feature platform of five devices with
system gates ranging from 50K to 1.4M gates, and I/Os ranging from 108 to 502
I/Os, with density migration. The Spartan-3A FPGAs also support up to 576 Kbits of
fast-block RAM with byte-write enable, and up to 176 Kbits of distributed RAM.
Additionally, there are built-in multipliers for efficient DSP implementation and
Digital Clock Managers (DCMs) for system level clock management functions.
Advance Features
The advance features in the Spartan-3A platform include unique Device DNA
serial number, support for 26 I/O standards, enhanced Multi-Boot capability
with watchdog timer, dual power management modes, and Dynamic Input
Delay for precise data-to-clock centering. These advance features significantly
help shorten design cycles and lower system cost.
SPARTAN-3 GENERATION FPGAs
Xilinx Spartan
-3A FPGA Platform
The World’s Lowest-Cost I/O Optimized FPGAs
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