參數(shù)資料
型號: XC3S200AN-4FT256I
廠商: Xilinx Inc
文件頁數(shù): 54/123頁
文件大小: 0K
描述: IC FPGA SPARTAN 3AN 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3AN
LAB/CLB數(shù): 448
邏輯元件/單元數(shù): 4032
RAM 位總計: 294912
輸入/輸出數(shù): 195
門數(shù): 200000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
36
Output Propagation Times
Table 27: Timing for the IOB Output Path
Symbol
Description
Conditions
Device
Speed Grade
Units
-5
-4
Max
Clock-to-Output Times
TIOCKP
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.87
3.13
ns
Propagation Times
TIOOP
The time it takes for data to travel from
the IOB’s O input to the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.78
2.91
ns
Set/Reset Times
TIOSRP
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
3.63
3.89
ns
TIOGSRQ
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
8.62
9.65
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
2.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 29.
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