參數(shù)資料
型號(hào): XC3164A-3PC84C
廠(chǎng)商: Xilinx Inc
文件頁(yè)數(shù): 22/76頁(yè)
文件大?。?/td> 0K
描述: IC LOGIC CL ARRAY 6400GAT 84PLCC
產(chǎn)品變化通告: XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標(biāo)準(zhǔn)包裝: 15
系列: XC3000A/L
LAB/CLB數(shù): 224
RAM 位總計(jì): 46064
輸入/輸出數(shù): 70
門(mén)數(shù): 4500
電源電壓: 4.25 V ~ 5.25 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 84-LCC(J 形引線(xiàn))
供應(yīng)商設(shè)備封裝: 84-PLCC
其它名稱(chēng): 122-1045
R
November 9, 1998 (Version 3.1)
7-31
XC3000 Series Field Programmable Gate Arrays
7
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
D/P
RESET
X5993
FPGA
General-
Purpose
User I/O
Pins
+5 V
M0
M1
PWRDWN
CCLK
DIN
STRB
D0
D1
D2
D3
D4
D5
D6
D7
RESET
I/O
Port
Micro
Computer
DOUT
HDC
LDC
M2
...
Other
I/O Pins
INIT
+5 V
5 k
If Readback is
Activated, a
5-k
Resistor is
Required in
Series with M1
*
Optional
Daisy-Chained
LCAs with
Different
Configurations
*
Figure 29: Slave Serial Mode Circuit Diagram
Product Obsolete or Under Obsolescence
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