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參數(shù)資料
| 型號(hào)： | XC3064L-8PC84C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 224 CLBS, 4000 GATES, 80 MHz, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 38/76頁(yè) |
| 文件大?。?/td> | 731K |
| 代理商： | XC3064L-8PC84C |
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R
XC3000 Series Field Programmable Gate Arrays
7-40
November 9, 1998 (Version 3.1)
Pin Functions During Configuration
Configuration Mode <M2:M1:M0>
***
**
****
SLAVE
SERIAL
<1:1:1>
MASTER-
SERIAL
<0:0:0>
PERIPH
<1:0:1>
MASTER-
HIGH
<1:1:0>
MASTER-
LOW
<1:0:0>
44
PLCC
64
VQFP
68
PLCC
84
PLCC
84
PGA
100
PQFP
100
VQFP
TQFP
132
PGA
144
TQFP
160
PQFP
175
PGA
176
TQFP
208
PQFP
User
Function
POWR
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
7
17
10
12
B2
29
26
A1
1
159
B2
1
3
POWER
DWN
(1)
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
M1 (LOW) (I)
M0 (LOW) (I)
M2 (LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
M1 (LOW) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
M1 (HIGH) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
M1 (LOW) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
16
17
18
19
20
22
23
26
27
28
31
32
33
34
36
40
41
47
48
49
50
51
52
53
54
55
57
58
59
60
61
62
63
64
1
2
3
4
25
26
27
28
30
34
35
43
44
45
46
47
48
49
50
51
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
2
3
4
5
6
7
8
9
31
32
33
34
36
42
43
53
54
55
56
57
58
60
61
62
65
66
67
70
71
72
73
74
75
76
77
78
81
82
83
84
2
3
4
5
8
9
10
11
J2
L1
K2
K3
L3
K6
J6
L11
K10
J10
K11
J11
H10
F10
G10
G11
F11
E11
E10
D10
C11
B11
C10
A11
B10
B9
A10
A9
B6
B7
A7
C7
A6
A5
B5
C5
A3
A2
B3
A1
52
54
56
57
59
65
66
76
78
80
81
82
83
87
88
89
92
93
94
98
99
100
1
2
5
6
8
9
12
13
14
15
17
18
19
20
23
24
25
26
49
51
53
54
56
62
63
73
75
77
78
79
80
84
85
86
89
90
91
95
96
97
98
99
2
3
5
6
9
10
11
12
14
15
16
17
20
21
22
26
B13
A14
C13
B14
D14
G14
H12
M13
P14
N13
M12
P13
N11
M9
N9
N8
N7
P6
M6
M5
N4
N2
M3
P1
M2
N1
L2
L1
K1
J2
H1
H2
G2
G1
F2
E1
D1
D2
B1
C2
36
38
40
41
45
53
55
69
71
73
74
75
78
84
85
88
92
93
96
102
103
106
107
108
111
112
115
116
119
120
123
124
128
129
133
134
137
138
141
142
40
42
44
45
49
59
61
76
78
80
81
82
86
92
93
96
102
103
106
114
115
119
120
121
124
125
128
129
132
133
136
137
141
142
147
148
151
152
155
156
B14
B15
C15
E14
D16
H15
J14
P15
R15
R14
N13
T14
P12
T11
R10
R9
P8
R8
R7
R5
P5
R3
N4
R2
P2
M3
P1
N1
M1
L2
K2
K1
H2
H1
F2
E1
D1
C1
E3
C2
45
47
49
50
54
65
67
85
87
89
90
91
96
102
103
108
112
113
118
124
125
130
131
132
135
136
140
141
146
147
150
151
156
157
164
165
169
170
173
174
48
50
56
57
61
77
79
100
102
107
109
110
115
122
123
128
132
133
138
145
146
151
152
153
161
162
165
166
172
173
178
179
184
185
192
193
199
200
203
204
RDATA
RTRIG (I)
I/O
I/O
I/O
I/O
GND
XTL2 OR I/O
RESET (I)
PROGRAM (I)
I/O
XTL1 OR I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CCLK (I)
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
All Others
XC3x20A etc.
XC3x30A etc.
XC3x42A etc.
XC3x64A etc.
XC3x90A etc.
XC3195A
RESET (I)
DONE
RESET (I)
DONE
RESET (I)
DONE
DATA 7 (I)
RESET (I)
DONE
DATA 7 (I)
RESET (I)
DONE
DATA 7 (I)
30
DATA 6 (I)
DATA 5 (I)
CS0 (I)
DATA 4 (I)
DATA 3 (I)
CS1 (I)
DATA 2 (I)
DATA 1 (I)
RDY/BUSY
DATA 0 (I)
DOUT
CCLK (O)
WS (I)
CS2 (I)
DATA 6 (I)
DATA 5 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK (O)
A0
A1
A2
A3
A15
A4
A14
A5
A13
A6
A12
A7
A11
A8
A10
A9
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK (O)
A0
A1
A2
A3
A15
A4
A14
A5
A13
A6
A12
A7
A11
A8
A10
A9
DIN (I)
DOUT
CCLK (I)
DIN (I)
DOUT
CCLK (O)
38
39
40
5
6
7
9
10
11
12
13
14
15
16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X**
X**
X**
X
X
X
X
X
X
X
Notes:
*
(I)
**
***
****
Note
:
Generic I/O pins are not shown.
For a detailed description of the configuration modes, see
page 25
through
page 34
.
For pinout details, see
page 65
through
page 76
.
Represents a weak pull-up before and during configuration.
INIT is an open drain output during configuration.
Represents an input.
Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown.
Peripheral mode and master parallel mode are not supported in the PC44 package.
Pin assignments for the XC3195A PQ208 differ from those shown.
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not identical.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3064L-8PC84I | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3064L-8TQ144C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3064L-8PC84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3064L-8TQ144C | 功能描述:IC FPGA 3.3V C-TEMP 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC3064L-8TQ144I | 功能描述:IC FPGA 3.3V I-TEMP 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC3090 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families |
| XC3090-100CB164B | 制造商:Xilinx 功能描述: |
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