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      參數(shù)資料
      型號(hào): XC3064A-7PQ160C
      廠商: Xilinx Inc
      文件頁數(shù): 35/76頁
      文件大小: 0K
      描述: IC LOGIC CL ARRAY 6400GAT 160PQF
      產(chǎn)品變化通告: Product Discontinuation 27/Apr/2010
      標(biāo)準(zhǔn)包裝: 1
      系列: XC3000A/L
      LAB/CLB數(shù): 224
      RAM 位總計(jì): 46064
      輸入/輸出數(shù): 120
      門數(shù): 4500
      電源電壓: 4.75 V ~ 5.25 V
      安裝類型: 表面貼裝
      工作溫度: 0°C ~ 85°C
      封裝/外殼: 160-BQFP
      供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
      其它名稱: 122-1030
      R
      XC3000 Series Field Programmable Gate Arrays
      7-42
      November 9, 1998 (Version 3.1)
      XC3000A Absolute Maximum Ratings
      Note:
      Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
      stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
      Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
      periods of time may affect device reliability.
      XC3000A Global Buffer Switching Characteristics Guidelines
      Note: 1. Timing is based on the XC3042A, for other devices see timing calculator.
      Symbol
      Description
      Units
      VCC
      Supply voltage relative to GND
      –0.5 to +7.0
      V
      VIN
      Input voltage with respect to GND
      –0.5 to VCC +0.5
      V
      VTS
      Voltage applied to 3-state output
      –0.5 to VCC +0.5
      V
      TSTG
      Storage temperature (ambient)
      –65 to +150
      °C
      TSOL
      Maximum soldering temperature (10 s @ 1/16 in.)
      +260
      °C
      TJ
      Junction temperature plastic
      +125
      °C
      Junction temperature ceramic
      +150
      °C
      Speed Grade
      -7
      -6
      Description
      Symbol
      Max
      Units
      Global and Alternate Clock Distribution1
      Either: Normal IOB input pad through clock buffer
      to any CLB or IOB clock input
      Or: Fast (CMOS only) input pad through clock
      buffer to any CLB or IOB clock input
      TPID
      TPIDC
      7.5
      6.0
      7.0
      5.7
      ns
      TBUF driving a Horizontal Longline (L.L.)1
      I to L.L. while T is Low (buffer active)
      T
      ↓ to L.L. active and valid with single pull-up resistor
      T
      ↓ to L.L. active and valid with pair of pull-up resistors
      T
      ↑ to L.L. High with single pull-up resistor
      T
      ↑ to L.L. High with pair of pull-up resistors
      TIO
      TON
      TPUS
      TPUF
      4.5
      9.0
      11.0
      16.0
      10.0
      4.0
      8.0
      10.0
      14.0
      8.0
      ns
      BIDI
      Bidirectional buffer delay
      TBIDI
      1.7
      1.5
      ns
      Product Obsolete or Under Obsolescence
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