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參數(shù)資料
| 型號(hào)： | XC3064A-6PP132C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 224 CLBS, 4000 GATES, 135 MHz, PPGA132 |
| 封裝： | PLASTIC, PGA-132 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 48K |
| 代理商： | XC3064A-6PP132C |
2-165
Speed Grade
-7
-6
Description
Symbol
Min
Max
Min
Max
Units
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
1
T
ILO
5.1
5.6
4.1
4.6
ns
ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
8
T
CKO
4.5
4.0
ns
T
QLO
9.5
10.0
8.0
8.5
ns
ns
Set-up time before clock K
Logic Variables
A, B, C, D, E
FG Mode
F and FGM Mode
DI
EC
2
T
ICK
4.5
5.0
4.0
4.5
3.5
4.0
3.0
4.0
ns
ns
ns
ns
Data In
Enable Clock
4
6
T
DICK
T
ECCK
Hold Time after clock K
Logic Variables
Data In
Enable Clock
A, B, C, D, E
DI
EC
3
5
7
T
CKI
T
CKDI
T
CKEC
0
1.0
2.0
0
1.0
2.0
ns
ns
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
T
CH
T
CL
F
CLK
4.0
4.0
3.5
3.5
ns
ns
MHz
113.0
135.0
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
13
T
RPW
T
RIO
6.0
5.0
ns
ns
9
6.0
5.0
Global Reset (RESET Pad)*
RESET width (Low)
delay from RESET pad to outputs X or Y
T
MRW
T
MRQ
16.0
14.0
ns
ns
19.0
17.0
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
*Timing is based on the XC3042A, for other devices see XACT timing calculator.
Notes: The CLB K to Q output delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (T
CKDI
, #5) of any CLB on the same die.
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| XC3064A-6PQ160C | 制造商:Xilinx 功能描述: |
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| XC3064A-7PC84C0100 | 制造商:Xilinx 功能描述: |
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