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參數(shù)資料
| 型號： | XC3030 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Families |
| 中文描述： | 家庭邏輯單元陣列 |
| 文件頁數(shù)： | 7/50頁 |
| 文件大?。?/td> | 474K |
| 代理商： | XC3030 |
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2-109
Figure 4.
Configurable Logic Block.
Each CLB includes a combinatorial logic section, two flip-flops and a program
memory controlled multiplexer selection of function. It has.
five logic variable inputs A, B, C, D, and E
a direct data in DI
an enable clock EC
a clock (invertible) K
an asynchronous direct RESET RD
two outputs X and Y
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. The
XC3020 has 64 such blocks arranged in 8 rows and 8
columns. The XACT development system is used to com-
pile the configuration data which is to be loaded into the
internal configuration memory to define the operation and
interconnection of each block. User definition of CLBs and
their interconnecting networks may be done by automatic
translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 4. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the
Q
COMBINATORIAL
FUNCTION
LOGIC
VARIABLES
D
RD
G
F
DIN
G
F
QX
QY
DIN
G
F
G
QY
QX
F
Q
D
RD
ENABLE CLOCK
CLOCK
DIRECT
RESET
1 (ENABLE)
A
B
C
D
E
DI
EC
K
RD
Y
X
X3032
0 (INHIBIT)
(GLOBAL RESET)
CLB OUTPUTS
DATA IN
0
1
0
MUX
1
MUX
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3030100PC44C | 制造商:Xilinx 功能描述:XC3030-100PC44C |
| XC3030-100PC44C | 功能描述:IC LOGIC CL ARRAY 3000GAT 44PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC3030-100PC44I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC3030100PC68C | 制造商:XILINX 功能描述:New |
| XC3030-100PC68C | 功能描述:IC LOGIC CL ARRAY 3000GAT 68PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設(shè)備封裝:120-CPGA（34.55x34.55） |
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