
Virtex-II Platform FPGAs: Functional Description
R
DS031-2 (v3.5) November 5, 2007
Module 2 of 4
Product Specification
15
ple configurations.
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are
available:
ROM16x1,
ROM32x1,
ROM64x1,
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration.
Table 10 shows the
number of LUTs occupied by each configuration.
Figure 18: Distributed SelectRAM (RAM16x1S)
Figure 19: Single-Port Distributed SelectRAM
(RAM32x1S)
A[3:0]
D
DI
WS
WSG
WE
WCLK
RAM 16x1S
D
Q
RAM
WE
CK
A[4:1]
WG[4:1]
Output
Registered
Output
(optional)
(SR)
4
(BY)
DS031_02_100900
A[3:0]
D
WSG
F5MUX
WE
WCLK
RAM 32x1S
D Q
WE
WE0
CK
WSF
D
DI
WS
RAM
G[4:1]
A[4]
WG[4:1]
D
DI
WS
RAM
F[4:1]
WF[4:1]
Output
Registered
Output
(optional)
(SR)
4
(BY)
(BX)
4
DS031_03_110100
Figure 20: Dual-Port Distributed SelectRAM
(RAM16x1D)
Table 10: ROM Configuration
ROM
Number of LUTs
16 x 1
1
32 x 1
2
64 x 1
4
128 x 1
8 (1 CLB)
256 x 1
16 (2 CLBs)
A[3:0]
D
WSG
WE
WCLK
RAM 16x1D
WE
CK
D
DI
WS
RAM
G[4:1]
WG[4:1]
dual_port
RAM
dual_port
4
(BY)
DPRA[3:0]
SPO
A[3:0]
WSG
WE
CK
D
DI
WS
G[4:1]
WG[4:1]
DPO
4
DS031_04_110100
(SR)