參數(shù)資料
型號： XC2V500-6FGG256C
廠商： Xilinx Inc
文件頁數(shù)： 261/318頁
文件大小： 0K
描述： IC FPGA VIRTEX-II 500K 256-FBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標準包裝： 90
系列： Virtex®-II
LAB/CLB數(shù)： 768
RAM 位總計： 589824
輸入/輸出數(shù)： 172
門數(shù)： 500000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應商設備封裝： 256-FBGA（17x17）
Virtex-II Platform FPGAs: Functional Description
R
DS031-2 (v3.5) November 5, 2007
Module 2 of 4
Product Specification
39
07/16/02
2.0
Updated compatible input standards listed in Table 6.
09/26/02
2.1
Changed number of resources available to the XC2V40 device in Table 13.
Clarified Power On Reset information under Configuration Sequence.
12/06/02
2.1.1
Cosmetic edits.
05/07/03
2.1.2
Added qualification note to Figure 13, page 11.
Corrected sentence in section Input/Output Individual Options, page 4, to read “The
optional weak-keeper circuit is connected to each user I/O pad.”
Corrected typographical errors in Table 3 for names of HSTL_[x]_DCI_18 standards.
06/19/03
2.2
Removed Compatible Output Standards and Compatible Input Standards tables.
Output Standards. This table replaces deleted I/O standards tables.
08/01/03
3.0
All Virtex-II devices and speed grades now Production. See Table 13, Module 3.
10/14/03
3.1
-
Added SSTL18_I and SSTL18_II.
-
Corrected names of 1.8V HSTL_I-IV standards to “HSTL_I-IV_18”.
-
Corrected Input VREF for HSTL_III-IV_18 from 1.08V to 1.1V.
-
Changed “N/A” to “N/R” (no requirement).
-
Changed “N/A” to “N/R” (no requirement).
-
Added SSTL18_I_DCI, SSTL18_II_DCI, LVDS_33_DCI, LVDSEXT_33_DCI,
LVDS_25_DCI, and LVDSEXT_25_DCI.
-
Corrected Input VREF for HSTL_III-IV_18 from 1.08V to 1.1V.
Sections Slave-Serial Mode and Master-Serial Mode, page 36: Changed "rising" to
"falling" edge with respect to DOUT.
Added verbiage to section Bitstream Encryption, page 38: “For devices that support
this feature, please contact your sales representative for specific ordering part
number.”
03/29/04
3.2
Table 2, page 2, and Table 5, page 7: Removed LVDS_33_DCI and
LVDSEXT_33_DCI from tables.
Table 26, page 37: Updated bitstream lengths.
Section BUFGMUX, page 29: Corrected the definition of the "presently selected clock"
to be I0 or I1. Corrected signal names in Figure 44 and associated text from CLK0 and
CLK1 to I0 and I1.
Recompiled for backward compatibility with Acrobat 4 and above.
06/24/04
3.3
Table 1, page 1: Added example to Footnote (1) regarding VCCO rules for GTL and
GTLP.
Added reference to Pb-free package types in Figure 7, page 6.
03/01/05
3.4
Reassigned heading hierarchies for better agreement with content.
Table 2: Corrected VOD output voltages.
Table 26: Updated bitstream lengths.
11/05/07
3.5
Updated copyright statement and legal disclaimer.
Boundary-Scan (JTAG, IEEE 1532) Mode, page 37: Updated IEEE 1149.1 compliance
statement.
Date
Version
Revision
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XC2V500-6FGG456C 功能描述:IC FPGA VIRTEX-II 500K 456-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-II 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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XC2V6000-4BF957C 功能描述:IC FPGA VIRTEX II 3M 957-FCBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55）
XC2V6000-4BF957CES 制造商:Xilinx 功能描述:
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