Virtex-II Platform FPGAs: DC and Switching Characteristics
R
DS031-3 (v3.5) November 5, 2007
Module 3 of 4
Product Specification
38
Miscellaneous Timing Parameters
Frequency Synthesis
Parameter Cross Reference
Table 42: Miscellaneous Timing Parameters
Description
Symbol
Constraints
FCLKIN
Speed Grade
Units
-6
-5
-4
Time Required to Achieve LOCK
Using DLL outputs(1)
LOCK_DLL
LOCK_DLL_60
> 60MHz
20.0
μs
LOCK_DLL_50_60
50 - 60 MHz
25.0
μs
LOCK_DLL_40_50
40 - 50 MHz
50.0
μs
LOCK_DLL_30_40
30 - 40 MHz
90.0
μs
LOCK_DLL_24_30
24 - 30 MHz
120.0
μs
Using CLKFX outputs
LOCK_FX_MIN
10.0
ms
LOCK_FX_MAX
10.0
ms
Additional lock time with
fine-phase shifting
LOCK_DLL_FINE_SHIFT
50.0
μs
Fine-Phase Shifting
Absolute shifting range
FINE_SHIFT_RANGE
10.0
ns
Delay Lines
Tap delay resolution
DCM_TAP_MIN
30.0
ps
DCM_TAP_MAX
60.0
ps
Notes:
1.
"DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
Specification also applies to PSCLK.
Table 43: Frequency Synthesis
Attribute
Min
Max
CLKFX_MULTIPLY
2
32
CLKFX_DIVIDE
1
32
Table 44: Parameter Cross Reference
Libraries Guide
Data Sheet
DLL_CLKOUT_{MIN|MAX}_LF
CLKOUT_FREQ_{1X|2X|DV}_LF
DFS_CLKOUT_{MIN|MAX}_LF
CLKOUT_FREQ_FX_LF
DLL_CLKIN_{MIN|MAX}_LF
CLKIN_FREQ_DLL_LF
DFS_CLKIN_{MIN|MAX}_LF
CLKIN_FREQ_FX_LF
DLL_CLKOUT_{MIN|MAX}_HF
CLKOUT_FREQ_{1X|DV}_HF
DFS_CLKOUT_{MIN|MAX}_HF
CLKOUT_FREQ_FX_HF
DLL_CLKIN_{MIN|MAX}_HF
CLKIN_FREQ_DLL_HF
DFS_CLKIN_{MIN|MAX}_HF
CLKIN_FREQ_FX_HF