
Virtex-II Platform FPGAs: Pinout Information
R
DS031-4 (v3.5) November 5, 2007
Module 4 of 4
Product Specification
8
NA
CCLK
M13
NA
PROG_B
B1
NA
DONE
N12
NA
M0
N2
NA
M1
M2
NA
M2
M3
NA
TCK
B12
NA
TDI
C1
NA
TDO
C11
NA
TMS
A13
NA
PWRDWN_B
M12
NA
HSWAP_EN
A1
NA
RSVD
A2
NA
RSVD
B2
NA
VBATT
A12
NA
RSVD
B11
NA
VCCAUX
C2
NA
VCCAUX
N1
NA
VCCAUX
N13
NA
VCCAUX
B13
NA
VCCINT
H2
NA
VCCINT
L7
NA
VCCINT
H13
NA
VCCINT
C7
NA
GND
E1
NA
GND
G2
NA
GND
J1
NA
GND
J4
NA
GND
M5
NA
GND
L9
NA
GND
J11
NA
GND
H10
NA
GND
F13
NA
GND
E12
NA
GND
B9
NA
GND
C5
Notes:
1.
See
Table 4 for an explanation of the signals available on this pin.
Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
Pin Number
No Connect in the XC2V40