參數(shù)資料
型號: XC2S50E-6PQG208C
廠商: Xilinx Inc
文件頁數(shù): 38/108頁
文件大小: 0K
描述: IC SPARTAN-IIE FPGA 50K 208-PQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 24
系列: Spartan®-IIE
LAB/CLB數(shù): 384
邏輯元件/單元數(shù): 1728
RAM 位總計(jì): 32768
輸入/輸出數(shù): 146
門數(shù): 50000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1330
DS077-3 (v3.0) August 9, 2013
35
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Switching Characteristics
Internal timing parameters are derived from measuring
internal test patterns. Listed below are representative val-
ues. For more specific, more precise, and worst-case guar-
anteed data, use the values reported by the static timing
analyzer (TRACE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parame-
ters assume worst-case operating conditions (supply volt-
age and junction temperature). Values apply to all
Spartan-IIE devices unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)
Symbol
Description
Speed Grade
Units
All
-7
-6
Min
Max
TICKOFDLL
LVTTL global clock input to output delay using
output flip-flop for LVTTL, 12 mA, fast slew rate,
with DLL.
1.0
3.1
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
3.
DLL output jitter is already included in the timing calculation.
4.
For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Symbol
Description
Device
Speed Grade
Units
All
-7
-6
Min
Max
TICKOF
LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without DLL.
XC2S50E
1.5
4.4
4.6
ns
XC2S100E
1.5
4.4
4.6
ns
XC2S150E
1.5
4.5
4.7
ns
XC2S200E
1.5
4.5
4.7
ns
XC2S300E
1.5
4.5
4.7
ns
XC2S400E
1.5
4.6
4.8
ns
XC2S600E
1.6
4.7
4.9
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
3.
For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
相關(guān)PDF資料
PDF描述
AIMC-0805-R12J-T INDUCTOR MULTILAYER 120NH 0805
XC3S200-4VQG100I SPARTAN-3 FPGA 200K STD 100VQFP
XC3S200A-4VQG100I IC FPGA SPARTAN-3A 200K 100-VQFP
GBM10DCSN CONN EDGECARD 20POS DIP .156 SLD
GBM10DCSH CONN EDGECARD 20POS DIP .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S50E-6PQG208I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S50E-6TQ144C 功能描述:IC FPGA 1.8V 384 CLB'S 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA(27x27)
XC2S50E-6TQ144I 制造商:Xilinx 功能描述:IC SYSTEM GATE
XC2S50E-6TQ144Q 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述:
XC2S50E-6TQG144C 功能描述:IC SPARTAN-IIE FPGA 50K 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA(27x27)