參數(shù)資料
型號(hào)： XC2S50E-6FTG256C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 36/108頁(yè)
文件大小： 0K
描述： IC SPARTAN-IIE FPGA 50K 256FTBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-IIE
LAB/CLB數(shù)： 384
邏輯元件/單元數(shù)： 1728
RAM 位總計(jì)： 32768
輸入/輸出數(shù)： 182
門(mén)數(shù)： 50000
電源電壓： 1.71 V ~ 1.89 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
其它名稱(chēng)： 122-1328
DS077-3 (v3.0) August 9, 2013
33
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Power-On Requirements
Spartan-IIE FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can con-
sume more than ICCPO min., though this cannot adversely
affect reliability.
A maximum limit for ICCPO is not specified. Be careful when
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of ICCPO by limiting the supply current
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
Symbol
Description
Min(1)
Typ
Max
Units
ICCPO
Total VCCINT supply current
required during power-on
Commercial
XC2S50E - XC2S300E
After PCN(2)
300
-
mA
Before
PCN(2)
500
-
mA
XC2S400E - XC2S600E
500
-
mA
Industrial
XC2S50E - XC2S300E
After PCN(2)
500
-
mA
Before
PCN(2)
2
-
A
XC2S400E - XC2S600E
700
-
mA
TCCPO
VCCINT(3,4) ramp time
After PCN(2)
500
-
μs
Before PCN(2)
2
-
50
ms
IHSPO
AC current per pin during power-on in
hot-swap applications when
VIN > VCCO + 0.4V; duration < 10ns
After PCN(2)
-
±60
-
μA
Notes:
1.
The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 1.8V.
2.
Devices built after the Product Change Notice PCN 2002-05 (see
after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E
always have this mark. Devices before the PCN have an ‘S’ preceding the date code. Note that devices before the PCN are
measured with VCCINT and VCCO powering up simultaneously.
3.
The ramp time is measured from GND to 1.8V on a fully loaded board.
4.
VCCINT must not dip in the negative direction during power on.
5.
I/Os are not guaranteed to be disabled until VCCINT is applied.
6.
For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL(1)
–0.5
0.8
2.0
3.6
0.4
2.4
24
–24
LVCMOS2
–0.5
0.7
1.7
2.7
0.4
1.9
12
–12
LVCMOS18
–0.5
35% VCCO
65% VCCO
1.95
0.4
VCCO – 0.4
8
–8
PCI, 3.3V
–0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
Note (2)
GTL
–0.5
VREF – 0.05
VREF + 0.05
3.6
0.4
-
40
-
GTL+
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.6
-
36
-
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