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    參數(shù)資料
    

    


    


    
型號(hào)：
XC2S30-5VQG100C

    

    
廠商：
Xilinx Inc

    

    
文件頁(yè)數(shù)：
78/99頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC FPGA 2.5V 216 CLB'S 100-VQFP

    

    
標(biāo)準(zhǔn)包裝：
90

    

    
系列：
Spartan®-II

    

    
LAB/CLB數(shù)：
216
    		

    

    
邏輯元件/單元數(shù)：
972
    		

    

    
RAM 位總計(jì)：
24576
    		

    

    
輸入/輸出數(shù)：
60
    		

    

    
門數(shù)：
30000
    		

    

    
電源電壓：
2.375 V ~ 2.625 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
封裝/外殼：
100-TQFP
    		

    

    
供應(yīng)商設(shè)備封裝：
100-VQFP（14x14）
    		

    

    
產(chǎn)品目錄頁(yè)面：
599 (CN2011-ZH PDF)
    		

    

    
其它名稱：
122-1513-5
    		

    

    

    

	
    
    
    

    
    
	
    Spartan-II FPGA Family: Functional Description
    DS001-2 (v2.8) June 13, 2008
    Module 2 of 4
    Product Specification
    8
    R
    The three IOB registers function either as edge-triggered
    D-type flip-flops or as level-sensitive latches. Each IOB has
    a clock signal (CLK) shared by the three registers and
    independent Clock Enable (CE) signals for each register. In
    addition to the CLK and CE control signals, the three
    registers share a Set/Reset (SR). For each register, this
    signal can be independently configured as a synchronous
    Set, a synchronous Reset, an asynchronous Preset, or an
    asynchronous Clear.
    A feature not shown in the block diagram, but controlled by
    the software, is polarity control. The input and output buffers
    and all of the IOB control signals have independent polarity
    controls.
    Optional pull-up and pull-down resistors and an optional
    weak-keeper circuit are attached to each pad. Prior to
    configuration all outputs not involved in configuration are
    forced into their high-impedance state. The pull-down
    resistors and the weak-keeper circuits are inactive, but
    inputs may optionally be pulled up.
    The activation of pull-up resistors prior to configuration is
    controlled on a global basis by the configuration mode pins.
    If the pull-up resistors are not activated, all the pins will float.
    Consequently, external pull-up or pull-down resistors must
    be provided on pins required to be at a well-defined logic
    level prior to configuration.
    All pads are protected against damage from electrostatic
    discharge (ESD) and from over-voltage transients. Two
    forms of over-voltage protection are provided, one that
    permits 5V compliance, and one that does not. For 5V
    compliance, a zener-like structure connected to ground
    turns on when the output rises to approximately 6.5V. When
    5V compliance is not required, a conventional clamp diode
    may be connected to the output supply voltage, VCCO. The
    type of over-voltage protection can be selected
    independently for each pad.
    All Spartan-II FPGA IOBs support IEEE 1149.1-compatible
    boundary scan testing.
    Input Path
    A buffer In the Spartan-II FPGA IOB input path routes the
    input signal either directly to internal logic or through an
    optional input flip-flop.
    An optional delay element at the D-input of this flip-flop
    eliminates pad-to-pad hold time. The delay is matched to
    the internal clock-distribution delay of the FPGA, and when
    used, assures that the pad-to-pad hold time is zero.
    Each input buffer can be configured to conform to any of the
    low-voltage signaling standards supported. In some of
    these standards the input buffer utilizes a user-supplied
    threshold voltage, VREF. The need to supply VREF imposes
    constraints on which standards can used in close proximity
    to each other. See "I/O Banking," page 9.
    There are optional pull-up and pull-down resistors at each
    input for use after configuration.
    Output Path
    The output path includes a 3-state output buffer that drives
    the output signal onto the pad. The output signal can be
    routed to the buffer directly from the internal logic or through
    an optional IOB output flip-flop.
    The 3-state control of the output can also be routed directly
    from the internal logic or through a flip-flip that provides
    synchronous enable and disable.
    Each output driver can be individually programmed for a
    wide range of low-voltage signaling standards. Each output
    buffer can source up to 24 mA and sink up to 48 mA. Drive
    strength and slew rate controls minimize bus transients.
    In most signaling standards, the output high voltage
    depends on an externally supplied VCCO voltage. The need
    to supply VCCO imposes constraints on which standards
    can be used in close proximity to each other. See "I/O
    An optional weak-keeper circuit is connected to each
    output. When selected, the circuit monitors the voltage on
    the pad and weakly drives the pin High or Low to match the
    input signal. If the pin is connected to a multiple-source
    signal, the weak keeper holds the signal in its last state if all
    Table 3: Standards Supported by I/O (Typical Values)
    I/O Standard
    Input
    Reference
    Voltage
    (VREF)
    Output
    Source
    Voltage
    (VCCO)
    Board
    Termination
    Voltage
    (VTT)
    LVTTL (2-24 mA)
    N/A
    3.3
    N/A
    LVCMOS2
    N/A
    2.5
    N/A
    PCI (3V/5V,
    33 MHz/66 MHz)
    N/A
    3.3
    N/A
    GTL
    0.8
    N/A
    1.2
    GTL+
    1.0
    N/A
    1.5
    HSTL Class I
    0.75
    1.5
    0.75
    HSTL Class III
    0.9
    1.5
    HSTL Class IV
    0.9
    1.5
    SSTL3 Class I
    and II
    1.5
    3.3
    1.5
    SSTL2 Class I
    and II
    1.25
    2.5
    1.25
    CTT
    1.5
    3.3
    1.5
    AGP-2X
    1.32
    3.3
    N/A
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
XC2S30-5VQG100I
 制造商:Xilinx 功能描述:FPGA SPARTAN-II 30K GATES 972 CELLS 263MHZ 2.5V 100VTQFP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE

    

    
XC2S30-6CS144C
功能描述:IC FPGA 2.5V C-TEMP 144-CSBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）

    

    
XC2S30-6CS144I
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

    

    
XC2S30-6CSG144C
 制造商:Xilinx 功能描述:FPGA SPARTAN-II 30K GATES 972 CELLS 263MHZ 2.5V 144CSBGA - Trays

    

    
XC2S30-6CSG144I
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family

    

    
    
    
    
	
    	
    
    
     
     
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