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參數(shù)資料
| 型號： | XC2S200E-6FGG456C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 29/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPARTAN-IIE FPGA 200K 456FBGA |
| 標準包裝： | 60 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 1176 |
| 邏輯元件/單元數(shù)： | 5292 |
| RAM 位總計： | 57344 |
| 輸入/輸出數(shù)： | 289 |
| 門數(shù)： | 200000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 456-BBGA |
| 供應(yīng)商設(shè)備封裝： | 456-FBGA |
| 其它名稱： | 122-1323 |
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DS077-2 (v3.0) August 9, 2013
27
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Multiple Spartan-IIE FPGAs can be configured using the
Slave Parallel mode, and be made to start-up simultane-
ously. To configure multiple devices in this way, wire the indi-
vidual CCLK, Data, WRITE, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by asserting the CS pin of each device in turn and
writing the appropriate data. Sync-to-DONE start-up timing
is used to ensure that the start-up sequence does not begin
until all the FPGAs have been loaded. See Start-up,
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 21, page 28 shows a flowchart of the write sequence
used to load data into the Spartan-IIE FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
The timing for Slave Parallel mode is shown in Figure 26,
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or deasserted. Otherwise an abort
will be initiated, as in the next section.
1.
Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
2.
On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
3.
Repeat steps 1 and 2 until all the data has been sent.
4.
Deassert CS and WRITE.
Figure 20: Slave Parallel Configuration Circuit Diagram
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
INIT
CCLK
DATA[7:0]
WRITE
BUSY
CS(0)
Spartan-IIE
DONE
INIT
PROGRAM
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
INIT
CS(1)
Spartan-IIE
DS077-2_06_110102
GND
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