參數(shù)資料
型號： XC2S150-6FG256C
廠商： Xilinx Inc
文件頁數(shù)： 51/99頁
文件大小： 0K
描述： IC FPGA 2.5V C-TEMP 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-II
LAB/CLB數(shù)： 864
邏輯元件/單元數(shù)： 3888
RAM 位總計： 49152
輸入/輸出數(shù)： 176
門數(shù)： 150000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
55
R
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Symbol
Description
Device
Speed Grade
Units
-6
-5
Min
TPSDLL / TPHDLL
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,(1)
with DLL
All
1.7 / 0
1.9 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
DLL output jitter is already included in the timing calculation.
4.
A zero hold time listing indicates no hold time or a negative hold time.
5.
For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Symbol
Description
Device
Speed Grade
Units
-6
-5
Min
TPSFD / TPHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,(1)
without DLL
XC2S15
2.2 / 0
2.7 / 0
ns
XC2S30
2.2 / 0
2.7 / 0
ns
XC2S50
2.2 / 0
2.7 / 0
ns
XC2S100
2.3 / 0
2.8 / 0
ns
XC2S150
2.4 / 0
2.9 / 0
ns
XC2S200
2.4 / 0
3.0 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
A zero hold time listing indicates no hold time or a negative hold time.
4.
For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S150-6FG256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S150-6FG456C 功能描述:IC FPGA 2.5V C-TEMP 456-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S150-6FG456I 制造商:Xilinx 功能描述:
XC2S150-6FGG256C 制造商:Xilinx 功能描述:FPGA SPARTAN-II 150K GATES 3888 CELLS 263MHZ 2.5V 256FBGA - Trays 制造商:Xilinx 功能描述:FPGA, 864 CLBS, 150000 GATES, 263 MHz, PBGA256
XC2S150-6FGG256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family
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