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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | XC2S15-6VQ100C |
| 寤犲晢锛� | Xilinx Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 74/99闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA 2.5V C-TEMP 100-PQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | Spartan®-II |
| LAB/CLB鏁�(sh霉)锛� | 96 |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 432 |
| RAM 浣嶇附瑷�(j矛)锛� | 16384 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 60 |
| 闁€鏁�(sh霉)锛� | 15000 |
| 闆绘簮闆诲锛� | 2.375 V ~ 2.625 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 85°C |
| 灏佽/澶栨锛� | 100-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-VQFP锛�14x14锛� |
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Spartan-II FPGA Family: Pinout Tables
DS001-4 (v2.8) June 13, 2008
Module 4 of 4
Product Specification
76
R
VCCINT
-P85
P24
A9
P171
-
I/O
1
-
P23
D8
P172
24
I/O
1
-
P22
C8
P173
27
I/O
1
-
P174
30
I/O
1
-
P175
33
I/O
1
-
P176
36
GND
-
---
P177
-
I/O, VREF
1P86
P21
B8
P178
39
I/O
1
-
P179
42
I/O
1
-
P20
A8
P180
45
I/O
1
P87
P19
B7
P181
48
I, GCK2
1
P88
P18
A7
P182
54
GND
-
P89
P17
C7
P183
-
VCCO
1P90
P16
D7
P184
-
VCCO
0P90
P16
D7
P184
-
I, GCK3
0
P91
P15
A6
P185
55
VCCINT
-P92
P14
B6
P186
-
I/O
0
-
P13
C6
P187
62
I/O
0
-
P188
65
I/O, VREF
0P93
P12
D6
P189
68
GND
-
---
P190
-
I/O
0
-
P191
71
I/O
0
-
P192
74
I/O
0
-
P193
77
I/O
0
-
P11
A5
P194
80
I/O
0
-
P10
B5
P195
83
VCCINT
-
P94
P9
C5
P196
-
VCCO
0
---
P197
-
GND
-
P8
D5
P198
-
I/O
0
P95
P7
A4
P199
86
I/O
0
P96
P6
B4
P200
89
I/O
0
-
P201
92
XC2S30 Device Pinouts (Continued)
XC2S30 Pad Name
VQ100 TQ144 CS144 PQ208
Bndry
Scan
Function
Bank
I/O, VREF
0
P97
P5
C4
P203
95
I/O
0
-
P204
98
I/O
0
-
P4
A3
P205
101
I/O
0
P98
P3
B3
P206
104
TCK
-
P99
P2
C3
P207
-
VCCO
0
P100
P1
A2
P208
-
VCCO
7
P100
P144
B2
P208
-
04/18/01
Notes:
1.
IRDY and TRDY can only be accessed when using Xilinx
PCI cores.
2.
Additional XC2S30 Package Pins
VQ100
Not Connected Pins
P28
P29
--
11/02/00
TQ144
Not Connected Pins
P104
P105
-
11/02/00
CS144
Not Connected Pins
M3
N3
--
11/02/00
PQ208
Not Connected Pins
P7
P13
P38
P44
P55
P56
P60
P97
P112
P118
P143
P149
P165
P202
-
11/02/00
Notes:
1.
For the PQ208 package, P13, P38, P118, and P143, which
are Not Connected Pins on the XC2S30, are assigned to
VCCINT on larger devices.
XC2S30 Device Pinouts (Continued)
XC2S30 Pad Name
VQ100 TQ144 CS144 PQ208
Bndry
Scan
Function
Bank
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| AMM25DTKT-S288 | CONN EDGECARD 50POS .156 EXTEND |
| XC2S15-5VQ100C | IC FPGA 2.5V 96 CLB'S 100-VQFP |
| AMM24DSAI | CONN EDGECARD 48POS R/A .156 SLD |
| XC2S15-5VQ100I | IC FPGA 2.5V I-TEMP 100-VQFP |
| XC3S50A-5VQG100C | IC FPGA SPARTAN-3A 50K 100-VQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| XC2S15-6VQ100I | 鍒堕€犲晢:XILINX 鍒堕€犲晢鍏ㄧū:XILINX 鍔熻兘鎻忚堪:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S15-6VQG100C | 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:FPGA SPARTAN-II 15K GATES 432 CELLS 263MHZ 2.5V 100VTQFP - Trays |
| XC2S15-6VQG100I | 鍒堕€犲晢:XILINX 鍒堕€犲晢鍏ㄧū:XILINX 鍔熻兘鎻忚堪:Spartan-II FPGA Family |
| XC2S200 | 鍒堕€犲晢:XILINX 鍒堕€犲晢鍏ㄧū:XILINX 鍔熻兘鎻忚堪:Spartan-II FPGA Family |
| XC2S200-5 | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Telecomm/Datacomm |
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