參數(shù)資料
型號(hào)： XC2S15-6CS144C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 46/99頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 2.5V C-TEMP 144-CSBGA
標(biāo)準(zhǔn)包裝： 198
系列： Spartan®-II
LAB/CLB數(shù)： 96
邏輯元件/單元數(shù)： 432
RAM 位總計(jì)： 16384
輸入/輸出數(shù)： 86
門(mén)數(shù)： 15000
電源電壓： 2.375 V ~ 2.625 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-TFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-LCSBGA（12x12）
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
50
R
Revision History
Date
Version
Description
09/18/00
2.0
Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description.
03/05/01
2.1
Clarified guidelines for applying power to VCCINT and VCCO
09/03/03
2.2
The following changes were made:
"Serial Modes," page 20 cautions about toggling WRITE during serial configuration.
Maximum VIH values in Table 32 and Table 33 changed to 5.5V.
In "Boundary Scan," page 13, removed sentence about lack of INTEST support.
In Table 9, page 17, added note about the state of I/Os after power-on.
In "Slave Parallel Mode," page 23, explained configuration bit alignment to SelectMap
port.
06/13/08
2.8
Added note that TDI, TMS, and TCK have a default pull-up resistor. Added note on maximum
daisy chain limit. Updated Figure 15 and Figure 18 since Mode pins can be pulled up to either
2.5V or 3.3V. Updated DLL section. Recommended using property or attribute instead of
primitive to define I/O properties. Updated description and links. Updated all modules for
continuous page, figure, and table numbering. Synchronized all modules to v2.8.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S15-6CS144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
XC2S15-6CSG144C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
XC2S15-6CSG144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
XC2S15-6FG256C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
XC2S15-6FG256I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
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