參數(shù)資料
型號(hào): XC2S100E-6FT256C
廠商: Xilinx Inc
文件頁數(shù): 96/108頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V 600 CLB'S 256-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-IIE
LAB/CLB數(shù): 600
邏輯元件/單元數(shù): 2700
RAM 位總計(jì): 40960
輸入/輸出數(shù): 182
門數(shù): 100000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
其它名稱: 122-1208
88
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O,
L#P_YY
0
A6
All
-
I/O,
L2P_YY
I/O,
L3P_YY
I/O,
L3P_YY
I/O,
L3P_YY
I/O,
L3P_YY
I/O,
L3P_YY
I/O, VREF
Bank 0,
L#N_YY
0
B6
All
I/O, VREF
Bank 0,
L2N_YY
I/O, VREF
Bank 0,
L3N_YY
I/O, VREF
Bank 0,
L3N_YY
I/O, VREF
Bank 0,
L3N_YY
I/O, VREF
Bank 0,
L3N_YY
I/O, VREF
Bank 0,
L3N_YY
I/O
0
C6
XC2S100E
-
I/O, L1P_Y
I/O
I/O, L#P
0
A5
XC2S100E
-
I/O, L1N_Y
I/O, L2P
I/O, L#N
0
B5
-
I/O, L2N
I/O
0
D6
-
I/O
I/O, L#P
0
B4
XC2S100E,
200E, 300E,
400E, 600E
-
I/O, L0P_Y
I/O, L1P
I/O, L1P_Y
I/O, L#N
0
C5
XC2S100E,
200E, 300E,
400E, 600E
XC2S200E,
300E,
400E, 600E
I/O, L0N_Y
I/O, L1N
I/O, VREF
Bank 0,
L1N_Y
I/O, VREF
Bank 0,
L1N_Y
I/O, VREF
Bank 0,
L1N_Y
I/O, VREF
Bank 0,
L1N_Y
I/O
0
A4
-
I/O
I/O, L#P
0
A3
XC2S150E,
400E, 600E
-
I/O, L0P_Y
I/O, L0P
I/O, L0P_Y
I/O, L#N
0
B3
XC2S150E,
400E, 600E
-
I/O, L0N_Y
I/O, L0N
I/O, L0N_Y
I/O
0
C4
-
I/O
0
D5
-
I/O
TCK
-
E6
-
TCK
Notes:
1.
Although designated with the _YY suffix in the XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these differential pairs are not
asynchronous in the XC2S400E.
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Device-Specific Pinouts: XC2S
Function
Bank
100E
150E
200E
300E
400E
600E
FG456 Differential Clock Pins
Clock
Bank
P
N
Pin
Name
Pin
Name
GCK0
4
AA12
GCK0, I
Y12
I/O (DLL), L#P
GCK1
5
AB12
GCK1, I
AB11
I/O (DLL), L#N
GCK2
1
A11
GCK2, I
A12
I/O (DLL), L#P
GCK3
0
C11
GCK3, I
B11
I/O (DLL), L#N
Additional FG456 Package Pins
VCCINT Pins
D4(1)
D19(1)
E5
E18
F6
F17
G7
G8
G15
G16
H7
H16
R7
R16
T7
T8
T15
T16
U6
U17
V5
V18
W4(1)
W19(1)
-
VCCO Bank 0 Pins
F7
F8
G9
G10
-
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XC2S100E6FT256I 制造商:Xilinx 功能描述:
XC2S100E-6FT256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
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XC2S100E-6FTG256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
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