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參數(shù)資料
| 型號： | XC2C64A-5VQG100C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CR-II CPLD 64MCELL 100-VQFP |
| 標準包裝： | 90 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 4.6ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 4 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 1500 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
| 包裝： | 托盤 |
| 配用： | 122-1536-ND - KIT STARTER SPARTAN-3E 122-1532-ND - KIT DEVELOPMENT SPARTAN 3ADSP |
CoolRunner-II CPLD Family
14
DS090 (v3.1) September 11, 2008
Product Specification
R
Absolute Maximum Ratings
Quality and Reliability Parameters
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Further Reading
Application Notes
(Bulletproof Design Practices)
(Timing Model)
(Logic Engine)
(Power Evaluation Equation for CoolRunner-II CPLDs)
(Low Power Design)
(Advanced Features)
(High Speed Design)
(Cross Point Switch)
Symbol
Parameter(1)
Min.
Max.
Unit
VCC(2)
Supply voltage relative to GND
–0.5
2.0
V
VI(3)
Input voltage relative to GND
–0.5
4.0
V
TA
Ambient Temperature (C-grade)
0
70
°C
Ambient Temperature (I-grade)
–40
85
°C
TJ(4)
Maximum junction temperature
–40
150
°C
TSTR
Storage temperature
–65
150
°C
Notes:
1.
Stresses above those listed might cause malfunction or permanent damage to the device. This is a stress rating only. Functional
operation at these or any other condition above those indicated in the operational and programming specification is not implied.
2.
The chip supply voltage should rise monotonically.
3.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins might undershoot to –2.0V or overshoot to 4.5 V, provided this overshoot or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. The I/O voltage can never exceed 4.0V.
4.
For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Symbol
Parameter
Min
Max
Units
TDR
Data retention
20
-
Years
NPE
Program/erase cycles (Endurance)
1,000
-
Cycles
VESD
Electrostatic discharge(1)
2,000
-
Volts
Notes:
1.
ESD is measured to 2000V using the human body model. Pins exposed to this limit can incur additional leakage current to
a maximum of 10
μA when driven to 3.9V.
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