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參數(shù)資料
| 型號(hào)： | XC2C32A-3CPG56C |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | FLASH PLD, 3 ns, PBGA56 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, CSP-56 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大?。?/td> | 264K |
| 代理商： | XC2C32A-3CPG56C |
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DS310 (v1.1) August 30, 2004
1
Advance Product Specification
1-800-255-7778
2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Optimized for 1.8V systems
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As fast as 3.0 ns pin-to-pin logic delays
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As low as 12
A quiescent current
Industry’s best 0.18 micron CMOS CPLD
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Optimized architecture for effective logic synthesis
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Multi-voltage I/O operation: 1.5V through 3.3V
Available in multiple package options
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32-land QFN with 21 user I/O
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44-pin PLCC with 33 user I/O
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44-pin VQFP with 33 user I/O
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56-ball CP BGA with 33 user I/O
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Pb-free available for all packages
Advanced system features
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Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
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IEEE1149.1 JTAG Boundary Scan Test
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Optional Schmitt-trigger input (per pin)
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I/O Banking
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RealDigital 100% CMOS product term generation
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Flexible clocking modes
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Optional DualEDGE triggered registers
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Global signal options with macrocell control
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
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Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
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Advanced design security
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Open-drain output option for Wired-OR and LED
drive
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Optional configurable grounds on unused I/Os
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Optional bus-hold, 3-state or weak pullup on
selected I/O pins
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Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
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PLA architecture
Superior pinout retention
100% product term routability across function
block
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Hot pluggable
Refer to the CoolRunner-II family data sheet for architec-
ture description.
Description
The CoolRunner-II 32-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of two Function Blocks interconnected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
The CoolRunner-II 32-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Table 1). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
0
XC2C32A CoolRunner-II CPLD
DS310 (v1.1) August 30, 2004
00
Advance Product Specification
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參數(shù)描述 |
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| XC2C32A-4CP56C | 制造商:Xilinx 功能描述:IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 750 GATES 32 MCRCLLS 500MHZ COMM 0.18UM 1 - Trays 制造商:Xilinx 功能描述:IC CPLD 32MC 3.8NS 56BGA 制造商:Xilinx 功能描述:IC CR-II CPLD 32MCELL 56-BGA |
| XC2C32A-4CPG56C | 功能描述:IC CPLD 32MCELL 21 I/O 56-CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán) |
| XC2C32A-4PC44C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XC2C32A-4PCG44C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XC2C32A-4QFG32C | 功能描述:IC CR-II CPLD 32MCELL 32-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán) |
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