參數(shù)資料
型號: XC164KM
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller with C166SV2 Core
中文描述: 16位單片機與C166SV2核心
文件頁數(shù): 58/62頁
文件大?。?/td> 567K
代理商: XC164KM
XC164KM
Derivatives
Electrical Parameters
Data Sheet
56
V1.0, 2005-11
4.3.2
The XC164KM’s Flash module delivers data within a fixed access time (see
Table 4-7
).
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
t
ACC
of the Flash array. The required Flash waitstates depend on the actual system
frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
On-chip Flash Operation
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), the Flash
accesses must be executed with 1 waitstate: ((1+1)
×
25 ns)
50 ns.
Table 4-8
indicates the interrelation of waitstates and system frequency.
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative, i.e. 40 MHz (or 20 MHz for XC164KM-xF20F devices).
Table 4-7
Parameter
Flash Characteristics
(Operating Conditions apply)
Symbol
Limit Values
Typ.
2
2)
200
2)
Unit
Min.
Max.
50
1)
5
500
Flash module access time
Programming time per 128-byte block
t
PR
Erase time per sector
t
ACC
CC –
CC –
CC –
1) The actual access time is influenced by the system frequency, see
Table 4-8
.
2) Programming and erase time depends on the system frequency. Typical values are valid for 40MHz.
ns
ms
ms
t
ER
Table 4-8
Required Waitstates
0 WS (WSFLASH = 00
B
)
1 WS (WSFLASH = 01
B
)
Flash Access Waitstates
Frequency Range
f
CPU
20 MHz
f
CPU
40 MHz
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