參數(shù)資料
型號: XA3S250E-4VQG100I
廠商: Xilinx Inc
文件頁數(shù): 9/37頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3E 250K 100-VQFP
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3E XA
LAB/CLB數(shù): 612
邏輯元件/單元數(shù): 5508
RAM 位總計: 221184
輸入/輸出數(shù): 66
門數(shù): 250000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
DS635 (v2.0) September 9, 2009
Product Specification
17
R
Table 16: Propagation Times for the IOB Input Path
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
-4 Speed
Grade
Units
Max
Propagation Times
TIOPLI
The time it takes for data to
travel from the Input pin through
the IFF latch to the I output with
no input delay programmed
LVCMOS25(2),
IFD_DELAY_VALUE = 0
0
All
2.25
ns
TIOPLID
The time it takes for data to
travel from the Input pin through
the IFF latch to the I output with
the input delay programmed
LVCMOS25(2),
IFD_DELAY_VALUE =
default software setting
2
XA3S100E
5.97
ns
3
XA3S250E
6.33
ns
2
XA3S500E
6.49
ns
5
XA3S1200E
8.15
ns
4
XA3S1600E
7.16
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in
2.
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 17.
Table 17: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Units
-4 Speed Grade
Single-Ended Standards
LVTTL
0.43
ns
LVCMOS33
0.43
ns
LVCMOS25
0
ns
LVCMOS18
0.98
ns
LVCMOS15
0.63
ns
LVCMOS12
0.27
ns
PCI33_3
0.42
ns
HSTL_I_18
0.12
ns
HSTL_III_18
0.17
ns
SSTL18_I
0.30
ns
SSTL2_I
0.15
ns
Differential Standards
LVDS_25
0.49
ns
BLVDS_25
0.39
ns
MINI_LVDS_25
0.49
ns
LVPECL_25
0.27
ns
RSDS_25
0.49
ns
DIFF_HSTL_I_18
0.49
ns
DIFF_HSTL_III_18
0.49
ns
DIFF_SSTL18_I
0.30
ns
DIFF_SSTL2_I
0.32
ns
Notes:
1.
The numbers in this table are tested using the methodology
presented in Table 19 and are based on the operating conditions
set forth in Table 6, Table 9, and Table 11.
2.
These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
Table 17: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Units
-4 Speed Grade
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