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參數(shù)資料
| 型號： | XA2C128-8CPG132Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 128MC 100 I/O 132CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | CoolRunner-II CPLD Starter Kit |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.0ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 8 |
| 宏單元數(shù)： | 128 |
| 門數(shù)： | 3000 |
| 輸入/輸出數(shù)： | 100 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-TFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 132-CSPBGA（8x8） |
| 包裝： | 托盤 |
XA2C128 CoolRunner-II Automotive CPLD
DS554 (v1.2) June 9, 2009
Product Specification
15
R
6.
Do not drive I/Os pins above the VCCIO assigned to its
I/O bank.
a.
The current flow can go into VCCIO and affect a user
voltage regulator.
b.
It can also increase undesired leakage current
associated with the device.
c.
If done for too long, it can reduce the life of the
device.
7.
Do not rely on the I/O states before the CPLD
configures. During power up, the CPLD I/Os may be
affected by internal or external signals.
8.
Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
9.
Ensure external JTAG terminations for TMS, TCK, TDI,
TDO should comply with the IEEE 1149.1. All Xilinx
CPLDs have internal weak pull-ups on TDI, TMS, and
TCK.
10. Attach all CPLD VCC and GND pins in order to have
necessary power and ground supplies around the
CPLD.
11. Decouple all VCC and VCCIO pins with capacitors of
0.01
μF and 0.1 μF closest to the pins for each
VCC/VCCIO-GND pair.
12. Configure I/Os properly. CoolRunner-II Automotive
CPLDs have I/O banks; therefore, signals must be
assigned to appropriate banks (LVCMOS33,
LVCMOS18 …)
Recommendations
The following recommendations are for all automotive appli-
cations.
1.
Use strict synchronous design (only one clocking event)
if possible. A synchronous system is more robust than
an asynchronous one.
2.
Include JTAG stakes on the PCB. JTAG stakes can be
used to test the part on the PCB. They add benefit in
reprogramming part on the PCB, inspecting chip
internals with INTEST, identifying stuck pins, and
inspecting programming patterns (if not secured).
3.
CoolRunner-II Automotive CPLDs work with any power
sequence, but it is preferable to power the VCCI (internal
VCC) before the VCCIO for the applications in which any
glitches from device I/Os are unwanted.
4.
Do not disregard report file warnings. Software
identifies potential problems when compiling, so the
report file is worth inspecting to see exactly how your
design is mapped onto the logic.
5.
Understand the Timing Report. This report file provides
a speed summary along with warnings. Read the timing
file (*.tim) carefully. Analyze key signal chains to
determine limits to given clock(s) based on logic
analysis.
6.
Review Fitter Report equations. Equations can be
shown in ABEL-like format, or can also be displayed in
Verilog or VHDL formats. The Fitter Report also
includes switch settings that are very informative of
other device behaviors.
7.
Let design software define pinouts if possible. Xilinx
CPLD software works best when it selects the I/O pins
and manages resources for users. It can spread signals
around and improve pin-locking. If users must define
pins, plan resources in advance.
8.
Perform a post-fit simulation for all speeds to identify
any possible problems (such as race conditions) that
might occur when fast-speed silicon is used instead of
slow-speed silicon.
9.
Distribute SSOs (Simultaneously Switching Outputs)
evenly around the CPLD to reduce switching noise.
10. Terminate high speed outputs to eliminate noise caused
by very fast rising/falling edges.
Additional Information
Additional information is available for the following CoolRunner-II topics:
XAPP784: Bulletproof CPLD Design Practices
XAPP375: Timing Model
XAPP376: Logic Engine
XAPP378: Advanced Features
XAPP382: I/O Characteristics
XAPP389: Powering CoolRunner-II
XAPP399: Assigning VREF Pins
These and other application notes can be accessed at:
Package specifications can be accessed at:
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| XA2C128-8VQG100Q | 功能描述:IC CPLD 128MCELL 80 I/O 100VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:160 系列:ispMACH® 4000V 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.5ns 電壓電源 - 內(nèi)部:3 V ~ 3.6 V 邏輯元件/邏輯塊數(shù)目:2 宏單元數(shù):32 門數(shù):- 輸入/輸出數(shù):30 工作溫度:-40°C ~ 130°C 安裝類型:表面貼裝 封裝/外殼:44-TQFP 供應(yīng)商設(shè)備封裝:44-TQFP（10x10） 包裝:托盤 |
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