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參數(shù)資料
| 型號： | XA-H4 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 16-bit microcontroller |
| 中文描述： | 單片16位微控制器 |
| 文件頁數(shù)： | 18/42頁 |
| 文件大?。?/td> | 225K |
| 代理商： | XA-H4 |
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Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
18
MMR Name
Reset
Value
Description
Address
Offset
Size
Read/Write
or Read Only
Memory Interface (MIF) Registers
8
280h
8
281h
8
282h
8
284h
8
285h
8
286h
8
288h
8
289h
8
28Ah
8
28Ch
8
28Dh
8
28Eh
8
290h
8
291h
8
292h
8
294h
8
295h
8
296h
8
2BEh
8
2BFh
B0CFG
B0AM
B0TMG
B1CFG
B1AM
B1TMG
B2CFG
B2AM
B2TMG
B3CFG
B3AM
B3TMG
B4CFG
B4AM
B4TMG
B5CFG
B5AM
B5TMG
MBCL
RFSH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MIF Bank 0 Config
MIF Bank 0 Base Address
MIF Bank 0 Timing Params
MIF Bank 1 Config
MIF Bank 1 Base Address
MIF Bank 1 Timing Params
MIF Bank 2 Config
MIF Bank 2 Base Address
MIF Bank 2 Timing Params
MIF Bank 3 Config
MIF Bank 3 Base Address
MIF Bank 3 Timing Params
MIF Bank 4 Config
MIF Bank 4 Base Address
MIF Bank 4 Timing Params
MIF Bank 5 Config
MIF Bank 5 Base Address
MIF Bank 5 Timing Params
MIF Memory Bank Configuration Lock Register
MIF Refresh Control
0Fh
00h
Miscellaneous Registers
16
2D0h
8
2D2h
Hi-Pri Soft Ints & Pin Mux Control Reg.
XInt2
R/W
R/W
Control bits for Hi-Priority Soft Ints, and Pin Mux
External Interrupt 2 Control
0000h
00h
FUNCTIONAL DESCRIPTION
The XA-H4 functions are described in the following sections.
Because all blocks are thoroughly documented in either the IC25 XA
Data Handbook or the XA-H4 User Manual only brief descriptions
are given in this datasheet in conjunction with references to the
appropriate document.
XA CPU
The CPU is a 30 MHz implementation of the standard XA CPU core.
See the XA Data Handbook(IC25) for details. The CPU core is
identical to the G3 core. See the caveat in the next paragraph about
the Bus Interface Unit.
Bus Interface Unit (BIU)
This is the internal Bus, not the bus at the pins. This internal bus
connects the CPU to the MIF (Memory and DRAM Controller.)
WARNING:
Immediately after reset, always write BTRH = 51h,
followed by BTRL = 40h, in that order. Once written, do not change
the values in these registers. Follow these two writes with five
NOPS. Never write to the BCR register. It comes out of reset
initialized to 07h, which is the only value that will work.
SU01273
XA CPU
MIF and DRAM
Controller
BIU
DMA
Channels
x8
External
Memory
and I/O Bus
Internal CPU Bus
Figure 1. XA CPU core BIU (Bus Interface Unit)
Timers 0 and 1
Timers 0 and 1 are the standard XA-G3 Timer 0 and 1. Each has an
associated I/O pin and interrupt. See the XA-G3 data sheet in the IC25
XA Data Handbook for details. Many XA derivatives include a standard
XA Timer 2 and standard UARTs. These blocks have been removed in
order to provide other functions on the XA-H4. There is no Timer 2 and
the UARTs have been replaced with full function USARTs.
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