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參數(shù)資料
| 型號： | X96012V14IZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 傳感器調(diào)節(jié)器 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 接口： | 2 線 |
| 電流 - 電源： | 15mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
22
FN8216.3
February 20, 2008
Data Protection
There are four levels of data protection designed into the
X96012:
1- Any Write to the device first requires setting of the WEL bit
in Control 6 register;
2- The Block Lock can prevent Writes to certain regions of
memory;
3- The Write Protection pin disables any writing to the
X96012;
4- The proper clock count, data bit sequence, and STOP
condition is required in order to start a nonvolatile write cycle,
otherwise the X96012 ignores the Write operation.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (LOW), any
Write operations to the X96012 is disabled, except the
writing of the WEL bit.
X96012
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