參數(shù)資料
型號: X96012
廠商: Intersil Corporation
英文描述: Universal Sensor Conditioner with Dual Look-up Table Memory and DACs(通用傳感器調(diào)節(jié)器,帶雙查找表存儲器及DACs)
中文描述: 通用傳感器護發(fā)雙查找表內(nèi)存和DAC(通用傳感器調(diào)節(jié)器,帶雙查找表存儲器及數(shù)模轉(zhuǎn)換器-)
文件頁數(shù): 6/23頁
文件大?。?/td> 353K
代理商: X96012
6
FN8216.3
February 20, 2008
NOTES:
14. LSB” is defined as V(VRef)/255, “Full-Scale” is defined as V(VRef).
15. Offset
ADC
: For an ideal converter, the first transition of its transfer curve occurs at
deviation between the measured first transition point and the ideal point. FSError
ADC
: For an ideal converter, the last transition of its transfer
curve occurs at
. Full-Scale Error is the amount of deviation between the measured last transition point and the ideal point,
after subtracting the Offset from the measured curve. DNL
ADC
: DNL is defined as the difference between the ideal and the measured code
transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Full-scale errors before
calculating DNL. INL
ADC
: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is
also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured transfer
curve is adjusted for Offset and Full scale errors before calculating INL.
above zero. Offset error is the amount of
A/D Converter Characteristics
(See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
0.5
x V(VRef)
255
[
]
254.5
x V
(
VRef
)
255
2-Wire Interface AC Characteristics
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNITS
f
SCL
SCL Clock Frequency
See “2-Wire Interface Test
Conditions” on page 6
See Figures 1, 2, 3.
1
(Note 18)
400
kHz
t
IN
(Note 2)
Pulse width Suppression Time at Inputs
50
ns
t
AA
(Note 2)
SCL Low to SDA Data Out Valid
900
ns
t
BUF
(Note 2)
Time the Bus Free Before Start of New
Transmission
1300
ns
t
LOW
Clock Low Time
1.3
1200
(Note 18)
μs
t
HIGH
Clock High Time
0.6
1200
(Note 18)
μs
t
SU:STA
Start Condition Set-up Time
600
ns
t
HD:STA
Start Condition Hold Time
600
ns
t
SU:DAT
Data In Set-up Time
100
ns
t
HD:DAT
Data In Hold Time
0
μs
t
SU:STO
Stop Condition Set-up Time
600
ns
t
DH
Data Output Hold Time
50
ns
t
R
(Note 2)
SDA and SCL Rise Time
20 +0.1Cb
(Note 16)
300
ns
t
F
(Note 2)
SDA and SCL Fall Time
20 +0.1Cb
(Note 16)
300
ns
t
SU:WP
(Note 2)
WP Set-up Time
600
ns
t
HD:WP
(Note 2)
WP Hold Time
600
ns
Cb (Note 2)
Capacitive Load for Each Bus Line
400
pF
2-Wire Interface Test Conditions
Input Pulse Levels
10% to 90% of V
CC
Input Rise and Fall Times, between 10% and 90%
10ns
Input and Output Timing Threshold Level
1.4V
External Load at Pin SDA
2.3k
Ω
to V
CC
and 100pF to V
SS
X96012
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