參數資料
| 型號： | X95840WV20IZ-2.7T1 |
| 廠商： | Intersil |
| 文件頁數： | 3/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL QUAD 10K OHM 20TSSOP |
| 標準包裝： | 1 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數： | 4 |
| 溫度系數： | 標準值 ±45 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 1237 (CN2011-ZH PDF) |
| 其它名稱： | X95840WV20IZ-2.7T1DKR |
11
FN8213.2
July 5, 2006
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
X95840 responds with an ACK. At this time, if the Data Byte
is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the X95840 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
X95840 enters its standby state (See Figure 17).
The byte at address 00001000 bin (8 decimal) determines if
the Data Byte is to be written to volatile and/or non-volatile
memory. See “Memory Description” on page 9.
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW) the
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0, 1, 2, 3, or 8 decimal, the
Data Byte is transferred to the appropriate Wiper Register
(WR) or to the Access Control Register, at the falling edge of
the SCL pulse that loads the last bit (LSB) of the Data Byte.
If the Address Byte is between 0 and 6 (inclusive), and the
Access Control Register is all zeros (default), then the STOP
condition initiates the internal write cycle to non-volatile
memory.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the X95840 responds with an ACK. Then the X95840
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eight bit of each
byte. The master terminates the read operation (issuing a
SDA Output from
Transmitter
SDA Output from
Receiver
8
1
9
START
ACK
SCL from Master
High Impedance
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
S
t
a
r
t
S
t
o
p
Identification
Byte
Address
Byte
Data
Byte
A
C
K
Signals from the
Master
Signals from the
X95840
A
C
K
1
0
1
00
A
C
K
Write
Signal at SDA
00 0 0
A2A1A0
FIGURE 17. BYTE WRITE SEQUENCE
X95840
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