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參數(shù)資料
| 型號： | X95840UV20IZ-2.7T1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL QUAD 50K OHM 20TSSOP |
| 標準包裝： | 1 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 ±45 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | X95840UV20IZ-2.7T1DKR |
10
FN8213.2
July 5, 2006
The X95840 is pre-programed with 80h in the four IVRs.
WR: Wiper Register, IVR: Initial value Register.
I2C Serial Interface
The X95840 supports a bidirectional I2C bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the X95840
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power up of the X95840 the SDA pin is in the
input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X95840 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power
up sequence and during internal non-volatile write cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
The X95840 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
X95840 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB in the Read/Write
bit. Its value is “1” for a Read operation, and “0” for a Write
operation. See Table 2.
TABLE 2. IDENTIFICATION BYTE FORMAT
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
8
—
Access Control
7
Reserved
6
5
4
General Purpose
Not Available
3
2
1
0
IVR3
IVR2
IVR1
IVR0
WR3
WR2
WR1
WR0
1
0
1
0
A2
A1
A0
R/W
(MSB)
(LSB)
Logic values at pins A2, A1, and A0 respectively
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
X95840
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