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      • 您現(xiàn)在的位置:買賣IC網(wǎng) > PDF目錄376448 > X9460KV14I (INTERSIL CORP) Dual Audio Control Digitally Controlled Potentiometer PDF資料下載
      參數(shù)資料
      型號(hào): X9460KV14I
      廠商: INTERSIL CORP
      元件分類: 數(shù)字電位計(jì)
      英文描述: Dual Audio Control Digitally Controlled Potentiometer
      中文描述: DUAL 33K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 32 POSITIONS, PDSO14
      封裝: PLASTIC, TSSOP-14
      文件頁(yè)數(shù): 6/16頁(yè)
      文件大?。?/td> 308K
      代理商: X9460KV14I
      第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
      6
      FN8203.2
      October 17, 2005
      Command Set and Register Description
      Device Addressing
      Following a start condition the master must output the Slave
      Byte Address of the slave it is accessing. The most
      significant four bits of the slave address are the device type
      identifier (refer to Figure 2). For the X9460 this is fixed as
      0101.
      The next three bits of the Slave Byte Address are the device
      address. The device address is defined by the A
      1
      - A
      0
      inputs.
      The X9460 compares the serial data stream with the Slave
      Byte Address; a successful compare is required for the
      X9460 to respond with an acknowledge. The A
      1
      - A
      0
      inputs
      can be actively driven by CMOS input signals or tied to V
      CC
      or V
      SS
      . The R/W bit sets the device for read or write
      operations. Note that the X9460 supports reads and writes to
      a single device on the 2-wire bus. If more than one X9460 is
      used on the same 2-wire bus, those devices must have
      unique device addresses and only writes are supported. You
      may not read from multiple devices or contention will result
      and the data is not valid.
      Command Set
      After a Slave Byte Address match, the next byte sent
      contains the Command and register pointer information. The
      four most significant bits are the Command. The next bit is a
      “X” (don’t care) set to zero.
      The Z
      D
      bit enables and disables the Zero Amplitude Wiper
      Switching circuit. When Z
      D
      =1, the wiper switches will turn on
      when close-to-zero amplitude is detected across the
      potentiometer pins. When Z
      D
      =0, this circuit is disabled. The
      last two bits, LT (left POT enable) and RT (right POT
      enable), select which of the two potentiometers is affected
      by the instruction.
      Several instructions require a three-byte sequence to
      complete. These instructions transfer data between the host
      and the X9460. These instructions are: Read Wiper Counter
      Register, Write Wiper Counter Register. The sequence of
      operations is shown in Figure 4 and 5. The four-byte
      command is used for write command for both right and left
      pots (Figure 6).
      Special Commands
      Increment/Decrement Instruction. The Increment/Decrement
      command is different from the other commands. Once the
      command is issued and the X9460 has responded with an
      acknowledge, the master can clock the selected wiper up
      and/or down. For each SCL clock pulse (t
      HIGH
      ) while SDA is
      HIGH, the selected wiper will move one resistor segment
      towards the R
      H
      terminal. Similarly, for each SCL clock pulse
      while SDA is LOW, the selected wiper will move one resistor
      segment towards the R
      L
      terminal. A detailed illustration of
      the sequence and timing for this operation are shown in
      Figures 7 and 8 respectively.
      Wiper Counter Register
      The X9460 contains two Wiper Counter Registers. The
      Wiper Counter Register output is decoded to select one of
      thirty-two switches along its resistor array. The Write Wiper
      Counter Register command directly sets the WCR to a
      value. The Increment/Decrement instruction steps the
      register value up or down one to multiple times.
      The WCR is a volatile register (Table 3) and is reset to the
      mute position (tap 0, “zero”) at power-up.
      TABLE 3. WIPER COUNTER REGISTERS, 5-bit - VOLATILE:
      WCR4
      WCR3
      WCR2
      The X9460 contains one 5-bit Wiper Counter Register for
      each DCP. (Two 5-bit registers in total.)
      1
      0
      0
      0
      A1
      A0
      R/W
      DEVICE TYPE
      IDENTIFIER
      DEVICE ADDRESS
      1
      FIGURE 2. SLAVE BYTE ADDRESS
      I1
      I2
      I3
      I0
      0
      Z
      D
      RT
      LT
      WIPER COUNTER
      SELECT
      INSTRUCTIONS
      this bit not used, set to 0
      FIGURE 3. COMMAND BYTE FORMAT
      WCR1
      WCR0
      (MSB)
      (LSB)
      X9460
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      X9460KV14I-2.7 功能描述:IC XDCP DUAL AUD 32T 33K 14TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:32 電阻(歐姆):50k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 50 ppm/°C 存儲(chǔ)器類型:易失 接口:3 線串行(芯片選擇,遞增,增/減) 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細(xì)型,TSOT-23-6 供應(yīng)商設(shè)備封裝:TSOT-23-6 包裝:帶卷 (TR)
      X9460KV14I-2.7T1 功能描述:IC XDCP DUAL AUD 32T 33K 14TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:32 電阻(歐姆):50k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 50 ppm/°C 存儲(chǔ)器類型:易失 接口:3 線串行(芯片選擇,遞增,增/減) 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細(xì)型,TSOT-23-6 供應(yīng)商設(shè)備封裝:TSOT-23-6 包裝:帶卷 (TR)
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