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參數(shù)資料
| 型號： | X9455YV24IZ-2.7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/19頁 |
| 文件大小： | 0K |
| 描述： | IC XDCP DUAL 256TAP 2.8K 24TS |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 2.8k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 9 線串行（芯片選擇，設(shè)備位址，動觸點(diǎn)位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
14
FN8202.1
July 28, 2006
All other address bits in the address byte must be set to “0”
during 2-wire write operations and their value should be
ignored when read.
Byte Write Operation
For any Byte Write operation, the X9455 requires the Slave
Address byte, an Address Byte, and a Data Byte (See Figure
7). After each of them, the X9455 responds with an ACK.
The master then terminates the transfer by generating a
STOP condition. At this time, if the write operation is to a
volatile register (WCR, or SR), the X9455 is ready for the
next read or write operation. If the write operation is to a
nonvolatile register (DR), and the WP pin is high, the X9455
begins the internal write cycle to the nonvolatile memory.
During the internal nonvolatile write cycle, the X9455 does
not respond to any requests from the master. The SDA
output is at high impedance.
The SR bits and WP pin determine the register being
accessed through the 2-wire interface. See Table 2 on page
9.
As noted before, any write operation to a Data Register
(DR), also transfers the contents of all the data registers in
that row to their corresponding WCR.
For example, to write 3Ahex to the Level 1 Data Register of
wiper 1A (DR1A1) the following sequence is required:
During the sequence of this example, WP pin must be high,
and A0, A1, and A2 pins must be low. When completed, the
DR1A1 register and the WCR1A of Wiper 1A will be set to
3Ah, and the other data registers in Row 1 will transfer their
contents to the respective WCRs.
S
t
a
r
t
S
t
o
p
Slave
Address
Status Register
Address
Data
A
C
K
A
C
K
Signal at SDA
Signals from
the Slave
Signals from
the Master
0
A
C
K
If bit 0 of data byte = 1,
DR contents move to WCR
during this ACK period
01 0 1
0 0 0 0 0 1 1 1
0 0 0 0 0 x x 1
DR select
FIGURE 6. STATUS REGISTER WRITE (USES STANDARD BYTE WRITE SEQUENCE TO SET UP ACCESS TO A DATA REGISTER)
TABLE 4. ADDRESSING FOR 2-WIRE INTERFACE ADDRESS
BYTE
ADDRESS (HEX)
CONTENTS
0
Wiper 0A
1
Wiper 1B
2
Wiper 1A
3
Wiper 0B
4
Not Used
5
Not Used
6
Not Used
7
Status Register
START
Slave Address
0101 0000
ACK
Address Byte
0000 0111
ACK
Data Byte
0000 0011
ACK
(note: at this ACK, the WCRs are all updated with their
respective DR.)
STOP
START
Slave Address
0101 0000
ACK
Address Byte
0000 0010
ACK
Data Byte
0011 1010
ACK
STOP
(Hardware Address = 000,
and a Write command)
(Indicates Status Register
address)
(Data Register Level 1 and
NVEnable selected)
(Hardware address = 000,
(Access Wiper 1A)
(Write Data Byte 3Ah)
Write command)
X9455
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