FN8199.0 March 11, 2005 Figure 3. Two-Byte Command Sequence Figure 4. Three-Byte Command Sequence The Increment/Decrement command is different f" />
參數(shù)資料
型號: X9438WV24I
廠商: Intersil
文件頁數(shù): 14/18頁
文件大?。?/td> 0K
描述: IC DUAL DCP + OPAMP 10K 24TSSOP
標(biāo)準(zhǔn)包裝: 75
系列: XDCP™
接片: 64
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 1238 (CN2011-ZH PDF)
5
FN8199.0
March 11, 2005
Figure 3. Two-Byte Command Sequence
Figure 4. Three-Byte Command Sequence
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9438 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the VH terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the VL terminal. A detailed illustration of the
sequence for this operation is shown in Figure 5.
Figure 5. Increment/Decrement Command Sequence
S
T
A
R
T
0101
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
0
P0
A
C
K
SCL
SDA
S
T
O
P
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1
I0
0
P0 R1 R0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
D5 D4 D3 D2
D1 D0
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
P1 P0 R1 R0
A
C
K
SCL
SDA
S
T
O
P
X
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
X9438
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