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參數(shù)資料
型號(hào): X9410YV24IZ-2.7
廠商: Intersil
文件頁(yè)數(shù): 4/21頁(yè)
文件大小: 0K
描述: IC XDCP DUAL 64-TAP 2.5K 24TSSOP
標(biāo)準(zhǔn)包裝: 62
系列: XDCP™
接片: 64
電阻(歐姆): 2.5k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 6 線 SPI(芯片選擇,設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
12
FN8193.2
October 12, 2006
A.C. TEST CONDITIONS
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the
third (last) power supply (VCC, V+ or V-) is stable until
the specific instruction can be issued. These parameters
are periodically sampled and not 100% tested.
Test Circuit #3 SPICE Macro Model
AC TIMING
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
Symbol
Parameter
Min.
Max.
Unit
fSCK
SSI/SPI clock frequency
2.0
MHz
tCYC
SSI/SPI clock cycle time
500
ns
tWH
SSI/SPI clock high time
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
s
tFI
SI, SCK, HOLD and CS input fall time
2
s
tDIS
SO output disable time
0
500
ns
tV
SO output valid time
100
ns
tHO
SO output hold time
0
ns
tRO
SO output rise time
50
ns
tFO
SO output fall time
50
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in High Z
100
ns
tLZ
HOLD high to output in Low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
20
ns
tCS
CS deselect time
2
s
tWPASU
WP, A0 and A1 setup time
0
ns
tWPAH
WP, A0 and A1 hold time
0
ns
X9410
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