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參數(shù)資料
| 型號： | X9252YV24IZ-2.7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL QUAD 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 2.8k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（芯片選擇，設(shè)備位址，增/減） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1237 (CN2011-ZH PDF) |
12
FN8167.2
November 14, 2005
To read or write the contents of a single Data Register or Wiper Register:
1.
Load the status register (using a write command) to select the row (See Figure 6)
Writing a 1, 3, 5, or 7 to the Status Register specifies that the subsequent read or write command will access a Data Register. This Status
Register operation also initiates a transfer of the contents of the selected data register to its associated WCR for all DCPs. So, for example,
writing ‘03h’ to the status register causes the value in DR01 to move to WCR0, DR11 to move to WCR1, DR21 to move to WCR2, and DR31
to move to WCR3.
Writing a 0 to bit ‘0’ of the Status Register specifies that the subsequent read or write command will access a Wiper Counter Register. Each
WCR can be written to individually, without affecting the contents of any other.
2.
Access the desired DR or WCR using a new write or read command (see Figure 7 for write and Figure 9 for read.)
Specify the desired column (DCP number) by sending the DCP address as part of this read or write command.
TABLE 2. REGISTER NUMBERING
STATUS REG (Note 1) (Addr: 07H)
REGISTERED SELECTED (Note 2)
RESERVED
BITS 7-3
DRSel1
bit 2
DRSel0
bit 1
NVEnable
bit 0
DCP0
DCP1
DCP2
DCP3
(Addr: 00h)
(Addr: 01h)
(Addr: 02h)
(Addr: 03h)
Reserved
X
0
WCR0
WCR1
WCR2
WCR3
0
1
DR00
DR10
DR20
DR30
0
1
DR01
DR11
DR21
DR31
1
0
1
DR02
DR12
DR22
DR32
1
DR03
DR13
DR23
DR33
S
t
a
r
t
S
t
o
p
Slave
Address
Status Register
Address
Data
A
C
K
A
C
K
Signal at SDA
Signals from
the Slave
Signals from
the Master
0
A
C
K
If bit 0 of data byte = 1,
DR contents move to WCR
during this ACK period
01 0 1
0 0 0 0 0 1 1 1
0 0 0 0 0 x x 1
DR select
FIGURE 6. STATUS REGISTER WRITE (USES STANDARD BYTE WRITE SEQUENCE TO SET UP ACCESS TO A DATA REGISTER)
X9252
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