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參數(shù)資料
| 型號： | X9221AWSZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 0K |
| 描述： | IC XDCP DUAL 10K 2-WIRE 20-SOIC |
| 標準包裝： | 1,000 |
| 系列： | XDCP™ |
| 接片： | 64 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction
Proceed
Issue STOP
NO
YES
Proceed
Issue STOP
NO
4
FN8163.2
August 30, 2006
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0-A3 inputs. The X9221A compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9221A to respond with an acknowledge.
Acknowledge Polling
The disabling of the inputs, during the internal nonvol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9221A initiates the inter-
nal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9221A is
still busy with the write operation no ACK will be
returned. If the X9221A has completed the write oper-
ation an ACK will be returned and the master can then
proceed with the next operation.
Flow 1. ACK Polling Sequence
Instruction Structure
The next byte sent to the X9221A contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.
Figure 2. Instruction Byte Format
t
I1
I2
I3
I0
0
P0
R1
R0
Potentiometer
Select
Register
Select
Instructions
The four high order bits define the instruction. The
sixth bit (P0) selects which one of the two potentiome-
ters is to be affected by the instruction. The last two
bits (R1 and R0) select one of the four registers that is
to be acted upon when a register oriented instruction
is issued.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM. The response of
the wiper to this action will be delayed tSTPWV. A
transfer from WCR’s current wiper position to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between either potentiometer and their associated
registers or it may occur between both of the potenti-
ometers and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9221A; either between the host and
one of the data registers or directly between the host
and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected data register. The
sequence of operations is shown in Figure 4.
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9221A has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
X9221A
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