參數(shù)資料
型號(hào): X84640EG-2.5
廠商: IC MICROSYSTEMS Sdn. Bhd.
元件分類(lèi): DRAM
英文描述: Advanced MPS⑩ Micro Port Saver EEPROM with Block Lock⑩ Protection
中文描述: 公安部⑩高級(jí)微端口保護(hù)程序區(qū)塊可鎖定的EEPROM⑩保護(hù)
文件頁(yè)數(shù): 2/22頁(yè)
文件大小: 571K
代理商: X84640EG-2.5
ObsoeePoduc
Data and command sequences are serially written to or
serially read from the device through the I/O pin.
X84160/640/128
2
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the out-
put buffer and to read data from the device on the I/O line.
Write Enable (WE)
The Write Enable input must be LOW to write either data
or command sequences to the device.
Data In/Data Out (I/O)
Write Protect (WP)
The Write Protect input controls the Hardware Write Pro-
tect feature. When WP is LOW and the nonvoltaile bit
WPEN is “1”, nonvolatile writes of the X84160/640/128
control register is disabled, but the part otherwise func-
tions normally. When WP is held HIGH, all functions,
including nonvolatile write operate normally. WP going
LOW while CS is still LOW will interrupt a write to the
X84160/640/128 control register. If the internal Write
cycle has already been initiated, WP going LOW will
have no effect on write.
The WP pin function is blocked when the WPEN bit in the
control register is “0”. This allows the user to install the
X84160/640/128 in a system with WP pin grounded and
still be able to write to the control register. The WP pin
functions will be enabled when the WPEN bit is set “1”.
PIN CONFIGURATIONS:
Drawings are to the same scale, actual package sizes are shown in inches:
VCC
OE
WE
CE
WP
VSS
1
3
4
8
6
5
8-LEAD SOIC
1
2
3
4
5
6
7
8
14
13
12
11
10
9
14-LEAD SOIC
CE
I/O
NC
NC
NC
WP
VSS
VCC
NC
NC
NC
NC
OE
WE
PIN NAMES
I/O
CE
OE
WE
WP
V
CC
V
SS
NC
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
Write Protect Input
Supply Voltage
Ground
No Connect
PACKAGE
SELECTION GUIDE
84160
8-Lead PDIP
8-Lead SOIC
8-Lead TSSOP
8-Lead CSP/BGA
8-Lead PDIP
8-Lead SOIC
20-Lead TSSOP
8-Lead CSP/BGA
8-Lead PDIP
14-Lead SOIC
28-Lead TSSOP
84640
84128
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20-LEAD TSSOP
CE
I/O
NC
NC
NC
WP
VSS
NC
VCC
NC
NC
NC
NC
OE
WE
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
19
18
17
16
15
28-LEAD TSSOP
NC
NC
NC
WP
V
SS
NC
NC
NC
NC
OE
WE
NC
NC
NC
I/O
CE
NC
V
CC
NC
CE
CE
NC
NC
NC
NC
NC
NC
21
22
23
24
25
26
27
28
X84160
X84640
X84128
.190 in.
.230 in.
.230 in.
.390 in.
.250 in.
.394 in.
.252 in.
. 252 in.
X84128
X84640
NC
OE
WP
VSS
NC
V
CE
I/O
1
2
3
4
8
7
6
5
8-LEAD TSSOP
.252 in.
8-LEAD PDIP
8-LEAD XBGA: Top View
NC
WE
OE
VSS
WP
VCC
I/O
CE
1
2
3
4
8
7
6
5
.
.078 in.
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