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X84041
Characteristics subject to change without notice.
4 of 13
REV 1.0 6/29/00
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restrictions. The processor is free to perform other
tasks on the bus whenever the chip enable pin (CE) is
HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be deter-
mined at any time by simply reading the state of the l/O
pin on the X84041. This pin is read when OE and CE
are LOW and WE is HIGH. During a nonvolatile write
cycle the l/O pin is LOW. When the nonvolatile write
cycle is complete, the l/O pin goes HIGH. A reset
sequence can also be issued during a nonvolatile write
cycle with the same result: I/O is LOW as long as a
nonvolatile write cycle is in progress, and l/O is HIGH
when the nonvolatile write cycle is done.
Figure 2. Write Sequence
CE
OE
WE
I/O (IN)
"0"
"0"
"1"
RESET
Load Address
Load Data
START
Nonvolatile
Write
A8
A7 A6 A5 A4 A3 A2 A1 A0
D3 D2 D1
I/O (OUT)
D0
D4
D5
D6
D7
X
X
X
X
X
X
X
Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
– The internal Write Enable latch is reset upon power-up.
– A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
– A special “start nonvolatile write” command sequence
is required to start a nonvolatile write cycle.
– The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
– The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
May change
from HIGH to
LOW
Will change
from LOW to
HIGH
Will change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance