參數(shù)資料
型號: X80013Q32I
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; Contact Termination:IDC; No. of Ports:3 RoHS Compliant: Yes
中文描述: 5-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝: 7 X 7 MM, 0.65 MM PITCH, QFN-32
文件頁數(shù): 5/25頁
文件大?。?/td> 548K
代理商: X80013Q32I
5
FN8149.0
January 13, 2005
Equivalent A.C. Output Load Circuit
t
RESET_E
Delay from PWRGD or ViGOOD to RESET
valid LOW
1
μ
s
t
QC
Delay from IGQ1 and IGQ0 to valid Gate pin
current
1
μ
s
t
SC_RETRY
Delay between Retries
85
100
115
ms
t
NF
Noise Filter for Overcurrent
4.5
5
5.5
μs
t
DPOR
Device Delay before Gate assertion
45
50
55
ms
t
SPOR
Delay after PWRGD and all ViGOOD signals
are active before RESET assertion
85
100
115
ms
t
DELAY1
Power Sequencing Time Delay
T
i
D1 = 0; T
i
D0 = 0
85
100
115
ms
t
DELAY2
t
DELAY3
t
DELAY4
t
TO
ViGOOD turn off time
50
ns
t
PDHLPG(1)
t
PDLHPG(1)
t
PGHLPG(1)
t
PGLHPG(1)
Delay from Drain good to PWRGD LOW
Gate = V
DD
1
μ
s
Delay from Drain fail to PWRGD HIGH
Gate = V
DD
1
μ
s
Delay from Gate good to PWRGD LOW
Drain = V
EE
1
μ
s
Delay from Gate fail to PWRGD HIGH
Drain = V
EE
1
μ
s
NOTE:
1.
This parameter is based on characterization data.
Electrical Specifications
(Standard Settings)
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A.C. Test Conditions
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing levels
V
CC
x 0.5
Output load
Standard output load
4.6k
RESET
30pF
V1GOOD,
5V
4.6k
30pF
V2GOOD,
V3GOOD,
V4GOOD
FAR
5V
PWRGD
X80010, X80011, X80012, X80013
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