參數(shù)資料
型號(hào)： X80012Q32I
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： 14 STR PE BLK RoHS Compliant: Yes
中文描述： 5-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝： 7 X 7 MM, 0.65 MM PITCH, QFN-32
文件頁(yè)數(shù)： 17/25頁(yè)
文件大小： 548K
代理商： X80012Q32I
17
FN8149.0
January 13, 2005
Hardshort Protection - FET Turn-on Retry
In the event on an over-current or hard short condition, the
X80010 includes a retry circuit. This circuit waits for 100ms,
then attempts to again turn on the FET. If the fault condition
still exists, the FET turns off and the sequence repeats. For
the X80010 and X80012, this process continues indefinitely
until the overcurrent condition does not exist. For the X80011
and X80013, this process repeats five times, only then will
keep the FET off and set the FAR pin active. After FAR is
asserted, it can be cleared using the master reset pin, MRH
(upon MRH assertion the FAR output is cleared) or cycling
the power on V
DD
.
If an overcurrent condition does not occur on any retry, the
gate pin proceeds to open at the user defined slew rate.
Gate Drive Output Slew Rate (Inrush Current)
Control
The gate output drives an external N-Channel FET. The
GATE pin goes high when no overcurrent, undervoltage or
overvoltage conditions exist.
The X80010 provides an I
GATE
current of 50μA to provide
on-chip slew rate control to minimize inrush current. This
I
GATE
current limits the inrush current and provides the best
charge time for a given load, while avoiding overcurrent
conditions.
For applications that require different ramp rates during
insertion and start-up and operations modes, the X80010
provides two external pins, IGQ1 and IGQ0, that allow the
user to switch to different GATE currents on-the-fly by
selecting one of four pre-selected I
GATE
currents. When
IGQ0 and IGQ1 are left unconnected, the gate current is
50μA. The other three settings are 10μA, 70μA and 150μA
(See Figure 36). Typically, the delay from IGQ1 and IGQ0
selection to a change in the GATE pin current is less than
1
μ
s.
Slew Rate (Gate) Control
As shown in Figure 37, this circuit block contains a current
source (I
GATE
) that drives the 50μA current into the GATE
pin. This current provides a controlled slew rate for the FET.
For applications that require different ramp rates during
insertion and operation or for applications where a different
gate current is desired, the X80010 provides two external
pins, IGQ1 and IGQ0, that allow the system to switch to a
different GATE current with pre-selected options.
The IGQ1 and IGQ0 pins can be used to select from one of
four set values.
Typically, the delay from IGQ1 and IGQ0 selection to a
change in the GATE pin current is less than 1
μ
s.
Gate Capacitor, Filtering and Feedback
In Figure 37, the FET control circuit includes an FET
feedback capacitor C
2
, which provides compensation for the
FET during turn on. The capacitor value depends on the
load, the FET gate current, and the maximum desired inrush
current.
The value of C2 can be selected with the following formula.
Where:
I
GATE
= FET Gate current
I
INRUSH
= Maximum desired inrush current
C
LOAD
= DC/DC bulk capacitance
I
overcurrent
I
GATE
I
GATE
= 50μA
70μA
50μA
10μA
T1
Time, ms
T2
T3
T4
T5
FIGURE 36. SELECTING I
GATE
CURRENT FOR SLEW RATE
CONTROL ON THE GATE PIN
IGQ1
PIN
IGQ0
PIN
CONTENTS
0
0
Defaults to gate current 50
μ
A
0
1
Gate Current is 10
μ
A
1
0
Gate Current is 70
μ
A
1
1
Gate Current is 150
μ
A
SENSE
V
EE
R
SENSE
LOAD
V
DD
=12V
Slew
Rate
Selection
Logic
GATE
10μA
50μA
70μA
I
INRUSH
DRAIN
100K
Gate Current
Quick Select
Logic
IGQ1
IGQ0
-48V
Control
Registers
150μA
100*
100nF*
* Optional Components
See Section “Gate Capacitor, Filtering and Feedback”
22K
3.3nF
C2
R2
FIGURE 37. SLEW RATE (INRUSH CURRENT) CONTROL
C2
I
-------------------------------------------
C
×
I
INRUSH
=
X80010, X80011, X80012, X80013
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