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參數(shù)資料
| 型號： | X80000 |
| 廠商： | Intersil Corporation |
| 英文描述： | Smart Power Plug Penta-Power Sequence Controller with Hot Swap |
| 中文描述： | 智能電源插頭五-序控制器電源熱插拔 |
| 文件頁數(shù)： | 4/37頁 |
| 文件大?。?/td> | 695K |
| 代理商： | X80000 |
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4
FN8148.0
March 18, 2005
V
OL
Output LOW Voltage
(RESET, V1GOOD, V2GOOD, V3GOOD,
V4GOOD, FAR, PWRGD)
I
OL
= 4.0mA
V
EE
+ 0.4
V
C
OUT
(Note 1)
Output Capacitance
(RESET, V1GOOD, V2GOOD, V3GOOD,
V4GOOD, FAR)
V
OUT
= 0V
8
pF
C
IN
(Note 1) Input Capacitance (MRH, MRC)
V
IN
= 0V
6
pF
V
OC
Overcurrent threshold
V
OC
= V
SENSE
- V
EE
45
50
55
mV
V
OCI
Overcurrent threshold (Insertion)
V
OC
= V
SENSE
- V
EE
PWRGD = HIGH
Initial Power Up condition
135
150
165
mV
V
OVR
Overvoltage threshold (rising)
X80000 Referenced to V
EE
3.85
3.90
3.95
V
X80001
3.49
3.54
3.59
V
V
OVF
Overvoltage threshold (falling)
X80000 Referenced to V
EE
3.82
3.87
3.92
V
X80001
3.46
3.51
3.56
V
V
UV1R
Undervoltage 1 threshold (rising)
Referenced to V
EE
BATT-ON = V
EE
2.19
2.24
2.29
V
V
UV1F
Undervoltage 1 threshold (falling)
2.16
2.21
2.26
V
V
UV2R
Undervoltage 2 threshold (rising)
Referenced to V
EE
BATT-ON = V
RGO
1.71
1.76
1.81
V
V
UV2F
Undervoltage 2 threshold (falling)
1.68
1.73
1.78
V
V
DRAINF
Drain sense voltage threshold (falling)
Referenced to V
EE
0.9
1
1.1
V
V
DRAINR
Drain sense voltage threshold (rising)
Referenced to V
EE
1.2
1.3
1.4
V
V
TRIP1
(Note 1)
EN1 Trip Point Voltage
Referenced to V
EE
V
RGO
÷ 2
V
V
TRIP2
(Note 1)
EN2 Trip Point Voltage
Referenced to V
EE
V
V
TRIP3
(Note 1)
EN3 Trip Point Voltage
Referenced to V
EE
V
V
TRIP4
(Note 1)
EN4 Trip Point Voltage
Referenced to V
EE
V
AC CHARACTERISTICS
t
FOC
Sense High to Gate Low
1.5
2.5
3.5
μ
s
t
FUV
Under Voltage conditions to Gate Low
0.5
1
1.5
μ
s
t
FOV
Overvoltage Conditions to Gate Low
1.0
1.5
2
μ
s
t
VFR
Overvoltage/undervoltage failure recovery time to
Gate =1V.
V
DD
does not drop below 3V, No
other failure conditions.
1.2
1.6
2
μ
s
t
BATT_ON
Delay BATT_ON Valid
100
ns
t
MRC
Minimum time high for reset valid on the MRC pin
5
μ
s
t
MRH
Minimum time high for reset valid on the MRH pin
5
μ
s
t
MRCE
Delay from MRC enable to PWRGD HIGH
No Load
1.0
1.6
μ
s
t
MRCD
Delay from MRC disable to PWRGD LOW
Gate is On, No Load
200
400
ns
t
MRHE
Delay from MRH enable to Gate Pin LOW
I
GATE
= 60μA, No Load
1.0
1.6
2.4
μ
s
Electrical Specifications
Standard Settings
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
X80000, X80001
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