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參數(shù)資料
| 型號： | X79002V20IT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NV SELECT OUT/MEM 20TSSOP |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | 417k |
8
FN8147.0
March 17, 2005
SPI INPUT TIMING
SPI INTERFACE TEST CONDITIONS
SERIAL INPUT TIMING
Notes: 1.
These parameters are periodically sampled and not 100% tested.
2.
tWC is the time from the rising edge of CS after a valid nonvolatile write sequence, to the end of the self-timed internal non-volatile write
cycle. It is the minimum cycle time to be allowed for any non-volatile write cycle by the user, unless the “WIP” bit is used to check for the
end of the write cycle.
Input Pulse Levels
10% to 90% of Vcc
Input Rise and Fall times, between 10% and 90%
10ns
Input and Output Timing Threshold Level
1.4V
External Load at pin SO
2.6k
to Vcc, 3.03k to Vss, and 10pF to Vss
Symbol
Parameter
Min.
Max.
Unit
fSCK
Clock Frequency
5
MHz
tCYC
Cycle Time
200
ns
tWH
Clock HIGH Time
80
ns
tWL
Clock LOW Time
80
ns
tLEAD
CS Lead Time
100
ns
tLAG
CS Lag Time
100
ns
tSU
Data Setup Time
20
ns
tH
Data Hold Time
20
ns
tRI (1)
Input Rise Time
20
ns
tFI (1)
Input Fall Time
20
ns
tCS
CS Deselect Time
100
ns
tWC (2)
Non-volatile Write Cycle Time
10
ms
...
CS
SCK
SI
SO
MSB
LSB
High Impedance
tLEAD
tH
tSU
tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
X79000, X79001, X79002
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