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參數(shù)資料
| 型號(hào)： | X79000V20I |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | NV DAC with Selectable Output Range and Memory |
| 中文描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 270K |
| 代理商： | X79000V20I |
8
FN8147.0
March 17, 2005
SPI INPUT TIMING
SPI INTERFACE TEST CONDITIONS
SERIAL INPUT TIMING
Notes: 1.
These parameters are periodically sampled and not 100% tested.
t
WC
is the time from the rising edge of CS after a valid nonvolatile write sequence, to the end of the self-timed internal non-volatile write
cycle. It is the minimum cycle time to be allowed for any non-volatile write cycle by the user, unless the “WIP” bit is used to check for the
end of the write cycle.
2.
Input Pulse Levels
Input Rise and Fall times, between 10% and 90%
Input and Output Timing Threshold Level
External Load at pin SO
10% to 90% of Vcc
10ns
1.4V
2.6k
to Vcc, 3.03k
to Vss, and 10pF to Vss
Symbol
f
SCK
t
CYC
t
WH
t
WL
t
LEAD
t
LAG
t
SU
t
H
t
RI
(1)
t
FI
(1)
t
CS
t
WC
(2)
Parameter
Min.
Max.
5
Unit
MHz
Clock Frequency
Cycle Time
200
ns
Clock HIGH Time
80
ns
Clock LOW Time
80
ns
CS Lead Time
100
ns
CS Lag Time
100
ns
Data Setup Time
20
ns
Data Hold Time
20
ns
Input Rise Time
20
ns
Input Fall Time
20
ns
CS Deselect Time
100
ns
Non-volatile Write Cycle Time
10
ms
...
t
WH
CS
SCK
SI
SO
MSB
LSB
High Impedance
t
LEAD
t
H
t
SU
t
FI
t
CS
t
LAG
t
CYC
t
WL
...
t
RI
X79000, X79001, X79002
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| X79001V20IT1 | 功能描述:IC DAC NV SELECT OUT/MEM 20TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| X79002 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NV DAC with Selectable Output Range and Memory |
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