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參數(shù)資料
| 型號(hào)： | X76F641XEG |
| 廠商： | IC MICROSYSTEMS SDN BHD |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 8K X 8 FLASH 5V PROM CARD, XMA8 |
| 封裝： | ROHS COMPLIANT, SMART CARD MODULE-8 |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大小： | 167K |
| 代理商： | X76F641XEG |
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X76F641
12
AC CHARACTERISTICS
AC Specifications
(Over the recommended operating conditions)
Notes:
1.
Typical values are for T
A
= 25C and V
CC
= 5.0V
Notes:
2.
C
b
= Total Capacitance of one bus line in pf.
Symbol
Parameter
Min
Typ
(1)
Max
Units
f
SCL
SCL Clock Frequency
0
400
KHz
t
IN
(1)
Pulse width of spikes which must be suppressed by the
input filter
50
100
ns
t
AA
SCL LOW to SDA Data Out Valid
0.1
0.3
0.9
∝
s
t
BUF
Time the bus must be free before a new transmit
can start
1.3
∝
s
t
LOW
Clock LOW Time
1.3
∝
s
t
HIGH
Clock HIGH Time
0.6
∝
s
t
SU:STA
Start Condition Setup Time
0.6
∝
s
t
HD:STA
Start Condition Hold Time
0.6
∝
s
t
SU:DAT
Data In Setup Time
100
ns
t
HD:DAT
Data In Hold Time
0
∝
s
t
SU:STO
Stop Condition Setup Time
0.6
∝
s
t
DH
Data Output Hold Time
50
300
ns
t
R
SDA and SCL Rise Time
20 + 0.1 x C
b
(2)
300
ns
t
F
SDA and SCL Fall Time
20 + 0.1 x C
b
(2)
300
ns
f
SCL_RST
SCL Clock Frequency during Response to Reset
400
kHz
t
SR
Device Select to RST active
200
ns
t
NOL
RST to SCL Non-Overlap
500
ns
t
RST
RST High Time
2.25
∝
s
t
SU:RST
Response to Reset Setup Time
1.25
∝
s
t
LOW_RST
Clock LOW during Response to Reset
1.25
∝
s
t
HIGH_RST
Clock HIGH during Response to Reset
1.25
∝
s
t
RDV
RST LOW to SDA Valid During Response to Reset
0
500
ns
t
CDV
CLK LOW to SDA Valid During Response to Reset
0
500
ns
t
DHZ
Device Deselect to SDA high impedance
0
500
ns
7025 FM T14
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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