參數(shù)資料
型號(hào)： X4045
元件分類： CPU監(jiān)測(cè)
英文描述： RTC Module With CPU Supervisor
中文描述： 時(shí)鐘模塊CPU監(jiān)控
文件頁(yè)數(shù)： 5/24頁(yè)
文件大小： 373K
代理商： X4045
5
FN8118.2
March 16, 2006
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4043/45 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When V
CC
exceeds the device V
TRIP
threshold value
for
200ms
(nominal)
RESET/RESET allowing the system to begin operation.
the
circuit
releases
Low Voltage Monitoring
During operation, the X4043/45 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
CC
returns and exceeds
V
TRIP
for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
(RESET/RESET) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two
nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “l(fā)ocked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
EEPROM Inadvertent Write Protection
When RESET/RESET goes active as a result of a low
voltage condition (V
CC
< V
TRIP
), any in-progress com-
munications are terminated. While V
CC
< V
TRIP
, no new
communications are allowed and no nonvolatile write
operation can start. Nonvolatile writes in-progress when
RESET/RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
TRIP
Programming
The X4043/45 is shipped with a standard V
CC
thresh-
old (V
TRIP
) voltage. This value will not change over
normal operating and storage conditions. However, in
applications where the standard V
TRIP
is not exactly
right, or if higher precision is needed in the V
TRIP
value, the X4043/45 threshold may be adjusted. The
procedure is described below, and uses the applica-
tion of a high voltage control signal.
Figure 2. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
SCL
SDA
.6μs
1.3μs
Start
Stop
Reset
WDT
0
1
2 3
4
5 6
7
SCL
SDA
A0h
0
1
2 3
4
5 6
7
01h
WP
V
P
= 15-18V
0
1
2 3
4
5 6
7
00h
X4043, X4045
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