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參數(shù)資料
| 型號： | X40420S14Z-A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Dual Voltage Monitor with Intergrated CPU Supervisor |
| 中文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-14 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 395K |
| 代理商： | X40420S14Z-A |
12
May 25, 2006
Figure 10. Byte Write Sequence
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the master
begins writing at location 10, and loads 12 bytes, then
the first 6 bytes are written to locations 10 through 15,
and the last 6 bytes are written to locations 0 through 5.
Afterwards, the address counter would point to location
6 of the page that was just written. If the master sup-
plies more than 16 bytes of data, then new data over-
writes the previous data, one byte at a time.
Figure 11. Page Write Operation
Figure 12. Writing 12 bytes to a 16-byte Page Starting at Location 10
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1
≤
n
≤
16)
1 0 1
0
0
address
n-1
address
10
6 Bytes
6 Bytes
address
= 5
address pointer
ends here
Addr = 6
X40420, X40421
相關PDF資料 |
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|---|---|
| X40420S14Z-B | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40420V14IZ-A | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40420V14Z-A | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40420V14Z-B | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40431V14-A | Triple Voltage Monitor with Integrated CPU Supervisor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X40420S14Z-AT1 | 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.9V 3000UA 14SOIC - Tape and Reel |
| X40420S14Z-B | 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.6V 3000UA 14SOIC - Rail/Tube |
| X40420S14Z-BT1 | 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.6V 3000UA 14SOIC - Tape and Reel |
| X40420V14-A | 功能描述:IC VOLT MON DUAL SUP/SW 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:100 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:- 復位:低有效 復位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:8-TSSOP 包裝:管件 |
| X40420V14-AT1 | 功能描述:IC VOLT MON DUAL SUP/SW 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:100 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:- 復位:低有效 復位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:8-TSSOP 包裝:管件 |
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