參數(shù)資料
型號(hào): X40420S14IZ-A
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-14
文件頁(yè)數(shù): 20/25頁(yè)
文件大?。?/td> 395K
代理商: X40420S14IZ-A
20
May 25, 2006
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Note:
(1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
Symbol
t
WC(1)
Parameter
Write Cycle Time
Min.
Typ.
(1)
5
Max.
10
Unit
ms
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1
Clk 9
Slave Address Byte
START
SCL
SDA
t
WC
8
th
Bit of Last Byte
ACK
Stop
Condition
Start
Condition
V2MON
V2FAIL
t
R
t
F
t
RPDX
V
RVALID
LOWLINE or
V
CC
or
V
TRIPX
t
RPDX
t
RPDX
t
RPDL
t
RPDL
t
RPDL
X = 1, 2
X40420, X40421
相關(guān)PDF資料
PDF描述
X40420S14IZ-B Dual Voltage Monitor with Intergrated CPU Supervisor
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X40420V14IZ-A Dual Voltage Monitor with Intergrated CPU Supervisor
X40420V14Z-A Dual Voltage Monitor with Intergrated CPU Supervisor
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