參數資料
型號： X4003S8I-2.7A
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： ; Peak Reflow Compatible (260 C):Yes
中文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝： 0.150 INCH, SOIC-8
文件頁數： 5/18頁
文件大?。?/td> 378K
代理商： X4003S8I-2.7A
X4003/X4005
Characteristics subject to change without notice.
5 of 18
REV 1.1.3 4/30/02
www.xicor.com
Figure 4. V
TRIP
Programming Sequence
V
TRIP
Programming
Apply 5V to V
CC
Decrement V
CC
(V
CC
= V
CC
–50mV)
RESET pin
goes active
Measured V
TRIP
-
Desired V
TRIP
DONE
Execute
Reset V
Sequence
Set V
CC
= V
CC
Applied =
Desired V
TRIP
Execute
Set V
TRIP
Sequence
New V
CC
Applied =
Old V
CC
applied + Error
Execute
Reset V
Sequence
New V
CC
Applied =
Old V
CC
Applied - Error
Error
≤
–Emax
-Emax < Error < Emax
YES
NO
Error
≥
Emax
Emax = Maximum Allowable V
TRIP
Error
Control Register
The control register provides the user a mechanism for
changing the watchdog timer settings. watchdog timer
bits are nonvolatile and do not change when power is
removed.
The control register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a control
register write operation. Only one data byte is allowed
for each register write operation. Prior to writing to the
control register, the WEL and RWEL bits must be set
using a two step process, with the whole sequence
requiring 3 steps. See "Writing to the Control Register"
below.
The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.
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