參數(shù)資料
型號(hào): X40031S14I-C
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: DIODE, STUD 165A 400VDIODE, STUD 165A 400V; Voltage, Vrrm:400V; Current, If av:165A; Current, Ifs max:2500A; Voltage, forward at If:1.5V; Case style:E14; Thread size:M12; Diode type:Standard recovery; Polarity, diode:Stud Cath
中文描述: 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: 0.150 INCH, SOIC-14
文件頁(yè)數(shù): 2/21頁(yè)
文件大小: 322K
代理商: X40031S14I-C
2
FN8114.0
April 28, 2005
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
*Voltage monitor requires V
CC
to operate. Others are independent of V
CC
PIN CONFIGURATION
Device
Expected System
Voltages
V
trip1
(V)
2.0-4.75*
4.55-4.65*
4.35-4.45*
2.95-3.05*
2.0-4.75*
4.55-4.65*
4.55-4.65*
4.55-4.65*
V
trip2
(V)
1.70-4.75
2.85-2.95
2.55-2.65
2.15-2.25
0.90-3.50
1.25-1.35
1.25-1.35
0.95-1.05
V
trip3
(V)
1.70-4.75
1.65-1.75
1.65-1.75
1.65-1.75
1.70-4.75
3.05-3.15
2.85-2.95
2.85-2.95
POR
(system)
X40030, X40031
-A
-B
-C
X40034, X40035
-A
-B
-C
5V; 3V or3.3V; 1.8V
5V; 3V; 1.8V
3.3V; 2.5V; 1.8V
RESET = X40030
RESET = X40031
5V; 3.3V; 1.5V
5V; 3V or 3.3V; 1.5V
5V; 3V or 3.3V; 1.2V
RESET = X40030
RESET = X40031
V3MON
WP
V
SS
V
CC
WDO
SDA
SCL
3
4
5
2
1
12
11
10
13
14
LOWLINE
NC
MR
RESET
7
6
8
9
V2MON
3
4
5
2
1
12
11
10
13
14
7
6
8
9
V3FAIL
V2FAIL
V3MON
WP
V
CC
WDO
SDA
SCL
V3FAIL
V
SS
LOWLINE
NC
MR
RESET
V2MON
V2FAIL
X40030, X40034
14-Pin SOIC, TSSOP
X40031, X40035
14-Pin SOIC, TSSOP
PIN DESCRIPTION
Pin
1
Name
V2FAIL
Function
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power up reset delay circuitry on this pin.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or
V
CC
when
not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the V
CC
input
(X40034, X40035).
Early Low V
CC
Detect.
This CMOS output signal goes LOW when
V
CC
< V
TRIP1
and goes high
when
V
CC
> V
TRIP1
.
No connect.
Manual Reset Input.
Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t
PURST
thereafter.
RESET Output.
(X40031, X40035) This open drain pin is an active LOW output which goes LOW
whenever V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active
for the programmed time period (t
PURST
) on power up. It will also stay active until manual reset is
released and for t
PURST
thereafter.
RESET Output.
(X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH
whenever V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active
for the programmed time period (t
PURST
) on power up. It will also stay active until manual reset is
released and for t
PURST
thereafter.
2
V2MON
3
LOWLINE
4
5
NC
MR
6
RESET/
RESET
X40030, X40031, X40034, X40035
相關(guān)PDF資料
PDF描述
X40034 DIODE, STANDARD, 165A, 1200V, STUD; Voltage, Vrrm:1200V; Current, If av:165A; Case style:E14; Current, Ifs max:2500A; Diode type:Standard recovery; Polarity, diode:Stud Cathode; Thread size:M12; Voltage, forward at If:1.5V RoHS Compliant: Yes
X40035 DIODE, STUD 320A 400VDIODE, STUD 320A 400V; Voltage, Vrrm:400V; Current, If av:320A; Current, Ifs max:6000A; Voltage, forward at If:1.4V; Case style:E15; Thread size:M16; Diode type:Standard recovery; Polarity, diode:Stud Cath
X40035-A Dual Voltage Monitor with Intergrated CPU Supervisor
X40035-C Dual Voltage Monitor with Intergrated CPU Supervisor
X40030V14-A Dual Voltage Monitor with Intergrated CPU Supervisor
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