參數(shù)資料
型號(hào)： X40020S14Z-B
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝： 0.150 INCH, ROHS COMPLIANT, SOIC-14
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 360K
代理商： X40020S14Z-B
13
FN8112.1
May 17, 2006
Read Operation
Prior to issuing the Slave Address Byte with the R/W bit
set to one, the master must first perform a “dummy” write
operation. The master issues the start condition and the
Slave Address Byte, receives an acknowledge, then
issues the Word Address Bytes. After acknowledging
receipts of the Word Address Bytes, the master immedi-
ately issues another start condition and the Slave
Address Byte with the R/W bit set to one. This is followed
by an acknowledge from the device and then by the eight
bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a
stop condition. See Figure 12 for the address, acknowl-
edge, and data transfer sequence.
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always “1011” when
accessing the control register and fault detection
register.
– two bits of “0”.
– one bit that becomes the MSB of the memory
address X
4
.
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. See Figure 13.
Figure 12. Read Sequence
0
Slave
Address
Byte
Address
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
1 0 1
0 0
1
1 1 1 1 1 1 1 1
X40020, 40021
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